Change in coreboot[master]: soc/intel/alderlake: Drop 100ms delay and do not poll Link Active

[John Zhao (Code Review)]

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51191 )

Change subject: soc/intel/alderlake: Drop 100ms delay and do not poll Link Active
......................................................................

soc/intel/alderlake: Drop 100ms delay and do not poll Link Active

Clone Tigerlake platform to drop the 100ms delay and do not poll Link
Active State for TBT PCIe root ports in order to improve the resume
time.

BUG=None
TEST=Built Alderlake coreboot image successfully.

Signed-off-by: John Zhao 
Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75
---
M src/soc/intel/alderlake/acpi/tcss_pcierp.asl
1 file changed, 0 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/51191/1

diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
index abca5d1..e03bf7f 100644
--- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
@@ -140,18 +140,6 @@
    	Local1 = L23R
    }
    STAT = 0x1
-
-	/* Wait for LA = 1 */
-	Local0 = 0
-	Local1 = LASX
-	While (Local1 == 0) {
-		If (Local0 > 20) {
-			Break
-		}
-		Sleep(5)
-		Local0++
-		Local1 = LASX
-	}
 }

/*
@@ -192,8 +180,6 @@
    If (PMEX == 1) {
    	PMEX = 0  /* Disable Power Management SCI */
    }
-
-	Sleep(100)  /* Wait for 100ms before return to OS starts any OS activities. */
 }

Method (_PS3, 0, Serialized)