Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43015 )
Change subject: mb/google/kahlee: Drop macro H1_PCH_INT ......................................................................
mb/google/kahlee: Drop macro H1_PCH_INT
This change drops H1_PCH_INT macro for GPIO_9 since it is the same across all variants. Also, the name differed from the schematics version `H1_PCH_INT_ODL` creating confusion.
Change-Id: I7b038426a984d8abc460a0da3ee1dc5559d7ad5f Signed-off-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c 2 files changed, 1 insertion(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/43015/1
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h index 6c1c941..8851072 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h @@ -11,9 +11,6 @@ # define MEM_CONFIG2 GPIO_131 # define MEM_CONFIG3 GPIO_132
-/* CR50 interrupt pin */ -#define H1_PCH_INT GPIO_9 - /* SPI Write protect */ #define CROS_WP_GPIO GPIO_122 #define GPIO_EC_IN_RW GPIO_15 diff --git a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c index 63625c4..1c87952 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c +++ b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c @@ -6,5 +6,5 @@
int tis_plat_irq_status(void) { - return gpio_interrupt_status(H1_PCH_INT); + return gpio_interrupt_status(GPIO_9); }
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43015 )
Change subject: mb/google/kahlee: Drop macro H1_PCH_INT ......................................................................
Patch Set 1:
Submitted based on feedback here: https://review.coreboot.org/c/coreboot/+/42874/4//COMMIT_MSG#7
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43015 )
Change subject: mb/google/kahlee: Drop macro H1_PCH_INT ......................................................................
Patch Set 1: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43015 )
Change subject: mb/google/kahlee: Drop macro H1_PCH_INT ......................................................................
Patch Set 1: Code-Review+1
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43015 )
Change subject: mb/google/kahlee: Drop macro H1_PCH_INT ......................................................................
mb/google/kahlee: Drop macro H1_PCH_INT
This change drops H1_PCH_INT macro for GPIO_9 since it is the same across all variants. Also, the name differed from the schematics version `H1_PCH_INT_ODL` creating confusion.
Change-Id: I7b038426a984d8abc460a0da3ee1dc5559d7ad5f Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43015 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c 2 files changed, 1 insertion(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, but someone else must approve Aaron Durbin: Looks good to me, approved
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h index 6c1c941..8851072 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h @@ -11,9 +11,6 @@ # define MEM_CONFIG2 GPIO_131 # define MEM_CONFIG3 GPIO_132
-/* CR50 interrupt pin */ -#define H1_PCH_INT GPIO_9 - /* SPI Write protect */ #define CROS_WP_GPIO GPIO_122 #define GPIO_EC_IN_RW GPIO_15 diff --git a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c index 63625c4..1c87952 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c +++ b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c @@ -6,5 +6,5 @@
int tis_plat_irq_status(void) { - return gpio_interrupt_status(H1_PCH_INT); + return gpio_interrupt_status(GPIO_9); }
-
Aaron Durbin (Code Review) -
Furquan Shaikh (Code Review)
-
Kyösti Mälkki (Code Review)