Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41938 )
Change subject: southbridge/intel/wildcatpoint: Add header files ......................................................................
southbridge/intel/wildcatpoint: Add header files
Relocate southbridge-related headers from soc to the southbridge scope. Note that the code in soc/intel/common expects to find `soc/nvs.h`.
And yes, some prototypes are now in the wrong place. This will be fixed in the next commits, once the soc/intel/broadwell subfolder is no more.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: If2bdef9b44ec8c93c1469074dc51a9964b4101ce Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/cpu.c M src/cpu/intel/broadwell/romstage.c M src/cpu/intel/broadwell/smmrelocate.c M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/auron/fadt.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/auron/variants/auron_paine/gpio.c M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/gpio.c M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/gpio.c M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/gpio.c M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/gpio.c M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/gpio.c M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/fadt.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/jecht/variants/guado/gpio.c M src/mainboard/google/jecht/variants/guado/pei_data.c M src/mainboard/google/jecht/variants/jecht/gpio.c M src/mainboard/google/jecht/variants/jecht/pei_data.c M src/mainboard/google/jecht/variants/rikku/gpio.c M src/mainboard/google/jecht/variants/rikku/pei_data.c M src/mainboard/google/jecht/variants/tidus/gpio.c M src/mainboard/google/jecht/variants/tidus/pei_data.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/intel/wtm2/fadt.c M src/mainboard/intel/wtm2/gpio.c M src/mainboard/intel/wtm2/pei_data.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/mainboard/purism/librem_bdw/fadt.c M src/mainboard/purism/librem_bdw/gpio.c M src/northbridge/intel/broadwell/acpi/broadwell.asl M src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/finalize.c M src/northbridge/intel/broadwell/igd.c M src/northbridge/intel/broadwell/memmap.c M src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/pei_data.c M src/northbridge/intel/broadwell/raminit.c M src/northbridge/intel/broadwell/refcode.c M src/northbridge/intel/broadwell/report_platform.c M src/northbridge/intel/broadwell/romstage.c M src/northbridge/intel/broadwell/systemagent.c D src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/systemagent.h R src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/acpi/pch.asl M src/southbridge/intel/wildcatpoint/adsp.c R src/southbridge/intel/wildcatpoint/adsp.h M src/southbridge/intel/wildcatpoint/bootblock.c R src/southbridge/intel/wildcatpoint/device_nvs.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/ehci.c R src/southbridge/intel/wildcatpoint/ehci.h M src/southbridge/intel/wildcatpoint/elog.c M src/southbridge/intel/wildcatpoint/gpio.c R src/southbridge/intel/wildcatpoint/gpio.h M src/southbridge/intel/wildcatpoint/hda.c M src/southbridge/intel/wildcatpoint/iobp.c R src/southbridge/intel/wildcatpoint/iobp.h R src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/lpc.c R src/southbridge/intel/wildcatpoint/lpc.h M src/southbridge/intel/wildcatpoint/me.c R src/southbridge/intel/wildcatpoint/me.h M src/southbridge/intel/wildcatpoint/me_status.c A src/southbridge/intel/wildcatpoint/nvs.h M src/southbridge/intel/wildcatpoint/pch.c R src/southbridge/intel/wildcatpoint/pch.h R src/southbridge/intel/wildcatpoint/pci_devs.h M src/southbridge/intel/wildcatpoint/pcie.c R src/southbridge/intel/wildcatpoint/pm.h M src/southbridge/intel/wildcatpoint/pmutil.c M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c R src/southbridge/intel/wildcatpoint/ramstage.h R src/southbridge/intel/wildcatpoint/rcba.h M src/southbridge/intel/wildcatpoint/sata.c R src/southbridge/intel/wildcatpoint/sata.h M src/southbridge/intel/wildcatpoint/serialio.c R src/southbridge/intel/wildcatpoint/serialio.h M src/southbridge/intel/wildcatpoint/smbus.c R src/southbridge/intel/wildcatpoint/smbus.h M src/southbridge/intel/wildcatpoint/smi.c M src/southbridge/intel/wildcatpoint/smihandler.c R src/southbridge/intel/wildcatpoint/soc_chip.h R src/southbridge/intel/wildcatpoint/spi.h M src/southbridge/intel/wildcatpoint/uart.c M src/southbridge/intel/wildcatpoint/xhci.c R src/southbridge/intel/wildcatpoint/xhci.h 115 files changed, 280 insertions(+), 279 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/41938/1
diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c index c052034..bd4eb63 100644 --- a/src/cpu/intel/broadwell/acpi.c +++ b/src/cpu/intel/broadwell/acpi.c @@ -15,14 +15,14 @@ #include <cpu/intel/turbo.h> #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/broadwell.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <intelblocks/cpulib.h>
/* diff --git a/src/cpu/intel/broadwell/bootblock.c b/src/cpu/intel/broadwell/bootblock.c index 3b041fe..3290eee 100644 --- a/src/cpu/intel/broadwell/bootblock.c +++ b/src/cpu/intel/broadwell/bootblock.c @@ -6,7 +6,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <halt.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/rcba.h> #include <cpu/intel/broadwell/broadwell.h> #include <delay.h>
diff --git a/src/cpu/intel/broadwell/chip.c b/src/cpu/intel/broadwell/chip.c index 16afcce..443faf4 100644 --- a/src/cpu/intel/broadwell/chip.c +++ b/src/cpu/intel/broadwell/chip.c @@ -2,10 +2,10 @@
#include <device/device.h> #include <device/pci.h> -#include <soc/acpi.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h>
static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, diff --git a/src/cpu/intel/broadwell/cpu.c b/src/cpu/intel/broadwell/cpu.c index f8189dd..f8132b5 100644 --- a/src/cpu/intel/broadwell/cpu.c +++ b/src/cpu/intel/broadwell/cpu.c @@ -18,11 +18,11 @@ #include <delay.h> #include <intelblocks/cpulib.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> #include <northbridge/intel/broadwell/broadwell.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <cpu/intel/common/common.h>
/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate diff --git a/src/cpu/intel/broadwell/romstage.c b/src/cpu/intel/broadwell/romstage.c index 03a7e96..35bb592 100644 --- a/src/cpu/intel/broadwell/romstage.c +++ b/src/cpu/intel/broadwell/romstage.c @@ -10,12 +10,12 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <timestamp.h> -#include <soc/gpio.h> -#include <soc/me.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/me.h> #include <northbridge/intel/broadwell/pei_data.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h> -#include <soc/spi.h> +#include <southbridge/intel/wildcatpoint/spi.h>
void fill_postcar_frame(struct postcar_frame *pcf) { diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c index ea38d15..dd96030 100644 --- a/src/cpu/intel/broadwell/smmrelocate.c +++ b/src/cpu/intel/broadwell/smmrelocate.c @@ -15,7 +15,7 @@ #include <console/console.h> #include <smp/node.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/broadwell.h>
diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index befe84e..616b51a 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -2,8 +2,8 @@
#include <arch/ioapic.h> #include <acpi/acpi.h> -#include <soc/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include <variant/thermal.h>
void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 2827cb1..dbcb25e 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -2,7 +2,7 @@
#include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h>
/* SPI Write protect is GPIO 16 */ #define CROS_WP_GPIO 58 diff --git a/src/mainboard/google/auron/fadt.c b/src/mainboard/google/auron/fadt.c index 653ebb4..e03d31b 100644 --- a/src/mainboard/google/auron/fadt.c +++ b/src/mainboard/google/auron/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <string.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <version.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index edbd9b6..eff3905 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -4,12 +4,12 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <elog.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include "ec.h" #include <variant/onboard.h>
diff --git a/src/mainboard/google/auron/variants/auron_paine/gpio.c b/src/mainboard/google/auron/variants/auron_paine/gpio.c index f2930e0..6a71ece 100644 --- a/src/mainboard/google/auron/variants/auron_paine/gpio.c +++ b/src/mainboard/google/auron/variants/auron_paine/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h>
const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c index 88c1c28..1217e1c 100644 --- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h>
diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index e937651..29f1b67 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/auron_yuna/gpio.c b/src/mainboard/google/auron/variants/auron_yuna/gpio.c index f2930e0..6a71ece 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/gpio.c +++ b/src/mainboard/google/auron/variants/auron_yuna/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h>
const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c index 88c1c28..1217e1c 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h>
diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index e937651..29f1b67 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/buddy/gpio.c b/src/mainboard/google/auron/variants/buddy/gpio.c index fcb63a4..8e09897 100644 --- a/src/mainboard/google/auron/variants/buddy/gpio.c +++ b/src/mainboard/google/auron/variants/buddy/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h>
const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index 823c968..5719a58 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h>
diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index 81bb828..7e5c1fe 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -8,7 +8,7 @@ #include <console/console.h> #include <device/device.h> #include <smbios.h> -#include <soc/pch.h> +#include <southbridge/intel/wildcatpoint/pch.h> #include <variant/onboard.h> #include <mainboard/google/auron/variant.h>
diff --git a/src/mainboard/google/auron/variants/gandof/gpio.c b/src/mainboard/google/auron/variants/gandof/gpio.c index 5b7ed82..051d921 100644 --- a/src/mainboard/google/auron/variants/gandof/gpio.c +++ b/src/mainboard/google/auron/variants/gandof/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h>
const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c index 88c1c28..1217e1c 100644 --- a/src/mainboard/google/auron/variants/gandof/pei_data.c +++ b/src/mainboard/google/auron/variants/gandof/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h>
diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index e937651..29f1b67 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index bc345da..98f489e 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <ec/google/chromeec/ec.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <smbios.h> #include <northbridge/intel/broadwell/romstage.h> #include <variant/onboard.h> diff --git a/src/mainboard/google/auron/variants/lulu/gpio.c b/src/mainboard/google/auron/variants/lulu/gpio.c index b049bde..aaf865c 100644 --- a/src/mainboard/google/auron/variants/lulu/gpio.c +++ b/src/mainboard/google/auron/variants/lulu/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h>
const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c index e88972e..447d0a0 100644 --- a/src/mainboard/google/auron/variants/lulu/pei_data.c +++ b/src/mainboard/google/auron/variants/lulu/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h>
diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index 7cf7e66..d4ed494 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index 98424d8..2d60232 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <ec/google/chromeec/ec.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <smbios.h> #include <northbridge/intel/broadwell/romstage.h> #include <variant/onboard.h> diff --git a/src/mainboard/google/auron/variants/samus/gpio.c b/src/mainboard/google/auron/variants/samus/gpio.c index 12e9e64..1416c46 100644 --- a/src/mainboard/google/auron/variants/samus/gpio.c +++ b/src/mainboard/google/auron/variants/samus/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h>
const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c index eef54d4..bd34d90 100644 --- a/src/mainboard/google/auron/variants/samus/pei_data.c +++ b/src/mainboard/google/auron/variants/samus/pei_data.c @@ -2,7 +2,7 @@
#include <stdint.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h>
diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index 213d4a5..5c45ca9 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c index baa0d52..2a04a83 100644 --- a/src/mainboard/google/auron/variants/samus/variant.c +++ b/src/mainboard/google/auron/variants/samus/variant.c @@ -2,8 +2,8 @@
#include <console/console.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h> #include <smbios.h> #include <variant/board_version.h> diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 50bd1e0..bcf6127 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -5,8 +5,8 @@ #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <device/device.h> -#include <soc/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include <variant/thermal.h>
void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 86d1e79..23298e7 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -5,8 +5,8 @@ #include <device/device.h> #include <vendorcode/google/chromeos/chromeos.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/sata.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/sata.h> #include "onboard.h"
#define GPIO_SPI_WP 58 diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c index 653ebb4..e03d31b 100644 --- a/src/mainboard/google/jecht/fadt.c +++ b/src/mainboard/google/jecht/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <string.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <version.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index 3d19f99..b31683f 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -7,7 +7,7 @@ #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> -#include <soc/pch.h> +#include <southbridge/intel/wildcatpoint/pch.h> #include "onboard.h"
static unsigned int search(char *p, u8 *a, unsigned int lengthp, diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 7072f8b..f407bcf 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -3,11 +3,11 @@ #include <acpi/acpi.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include "onboard.h"
int mainboard_io_trap_handler(int smif) diff --git a/src/mainboard/google/jecht/variants/guado/gpio.c b/src/mainboard/google/jecht/variants/guado/gpio.c index b4ffaa7..d3d44e2 100644 --- a/src/mainboard/google/jecht/variants/guado/gpio.c +++ b/src/mainboard/google/jecht/variants/guado/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h>
const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c index 1efb768..d624c83 100644 --- a/src/mainboard/google/jecht/variants/guado/pei_data.c +++ b/src/mainboard/google/jecht/variants/guado/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h>
diff --git a/src/mainboard/google/jecht/variants/jecht/gpio.c b/src/mainboard/google/jecht/variants/jecht/gpio.c index 92470cd..4aee5df 100644 --- a/src/mainboard/google/jecht/variants/jecht/gpio.c +++ b/src/mainboard/google/jecht/variants/jecht/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h>
const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c index 1efb768..d624c83 100644 --- a/src/mainboard/google/jecht/variants/jecht/pei_data.c +++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h>
diff --git a/src/mainboard/google/jecht/variants/rikku/gpio.c b/src/mainboard/google/jecht/variants/rikku/gpio.c index b4ffaa7..d3d44e2 100644 --- a/src/mainboard/google/jecht/variants/rikku/gpio.c +++ b/src/mainboard/google/jecht/variants/rikku/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h>
const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c index 1efb768..d624c83 100644 --- a/src/mainboard/google/jecht/variants/rikku/pei_data.c +++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h>
diff --git a/src/mainboard/google/jecht/variants/tidus/gpio.c b/src/mainboard/google/jecht/variants/tidus/gpio.c index 805b617..9c3d934 100644 --- a/src/mainboard/google/jecht/variants/tidus/gpio.c +++ b/src/mainboard/google/jecht/variants/tidus/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h>
const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c index 6af5d83..35dc2e7 100644 --- a/src/mainboard/google/jecht/variants/tidus/pei_data.c +++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h>
diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 960dbde..b601ea3 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -5,8 +5,8 @@ #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <device/device.h> -#include <soc/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include "thermal.h"
void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 459560c..c4470c6 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -3,7 +3,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/device.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
/* Compile-time settings for recovery mode. */ diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index 77231e2..b85eba74 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <string.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <version.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) diff --git a/src/mainboard/intel/wtm2/gpio.c b/src/mainboard/intel/wtm2/gpio.c index c779ef0..868e58e 100644 --- a/src/mainboard/intel/wtm2/gpio.c +++ b/src/mainboard/intel/wtm2/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h>
const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c index bcf091a..8795cf3 100644 --- a/src/mainboard/intel/wtm2/pei_data.c +++ b/src/mainboard/intel/wtm2/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h>
diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 9fc63cf..cc8e8e4 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> #include <northbridge/intel/broadwell/romstage.h> diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index 8383f63..8b719bd 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -2,8 +2,8 @@
#include <acpi/acpi.h> #include <arch/ioapic.h> -#include <soc/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/nvs.h>
void acpi_create_gnvs(global_nvs_t *gnvs) { diff --git a/src/mainboard/purism/librem_bdw/fadt.c b/src/mainboard/purism/librem_bdw/fadt.c index b756fb9..10c9b78 100644 --- a/src/mainboard/purism/librem_bdw/fadt.c +++ b/src/mainboard/purism/librem_bdw/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <string.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <version.h>
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) diff --git a/src/mainboard/purism/librem_bdw/gpio.c b/src/mainboard/purism/librem_bdw/gpio.c index 57afe56..555b069 100644 --- a/src/mainboard/purism/librem_bdw/gpio.c +++ b/src/mainboard/purism/librem_bdw/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h>
const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_INPUT, /* 0 */ diff --git a/src/northbridge/intel/broadwell/acpi/broadwell.asl b/src/northbridge/intel/broadwell/acpi/broadwell.asl index 258e6e7..12296cb 100644 --- a/src/northbridge/intel/broadwell/acpi/broadwell.asl +++ b/src/northbridge/intel/broadwell/acpi/broadwell.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h>
Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c index be389b7..89ff992 100644 --- a/src/northbridge/intel/broadwell/bootblock.c +++ b/src/northbridge/intel/broadwell/bootblock.c @@ -2,7 +2,7 @@
#include <arch/bootblock.h> #include <device/pci_ops.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/broadwell.h>
void bootblock_early_northbridge_init(void) diff --git a/src/northbridge/intel/broadwell/broadwell.h b/src/northbridge/intel/broadwell/broadwell.h index 8d71103..5f4ad6c 100644 --- a/src/northbridge/intel/broadwell/broadwell.h +++ b/src/northbridge/intel/broadwell/broadwell.h @@ -3,7 +3,7 @@ #ifndef __NORTHBRIDGE_INTEL_BROADWELL_BROADWELL_H__ #define __NORTHBRIDGE_INTEL_BROADWELL_BROADWELL_H__
-#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h>
#define SA_IGD_OPROM_VENDEV 0x80860406
diff --git a/src/northbridge/intel/broadwell/finalize.c b/src/northbridge/intel/broadwell/finalize.c index d258694..ccd3e74 100644 --- a/src/northbridge/intel/broadwell/finalize.c +++ b/src/northbridge/intel/broadwell/finalize.c @@ -6,11 +6,11 @@ #include <cpu/x86/smm.h> #include <reg_script.h> #include <spi-generic.h> -#include <soc/pci_devs.h> -#include <soc/lpc.h> -#include <soc/me.h> -#include <soc/rcba.h> -#include <soc/spi.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/me.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/spi.h> #include <northbridge/intel/broadwell/broadwell.h> #include <southbridge/intel/common/spi.h>
diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c index 3e47b53..6c0da56 100644 --- a/src/northbridge/intel/broadwell/igd.c +++ b/src/northbridge/intel/broadwell/igd.c @@ -16,10 +16,10 @@ #include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/pm.h> -#include <soc/ramstage.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/broadwell.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <security/vboot/vbnv.h> #include <northbridge/intel/broadwell/igd.h> #include <types.h> diff --git a/src/northbridge/intel/broadwell/memmap.c b/src/northbridge/intel/broadwell/memmap.c index c062d7d..ca8b105 100644 --- a/src/northbridge/intel/broadwell/memmap.c +++ b/src/northbridge/intel/broadwell/memmap.c @@ -6,7 +6,7 @@ #include <cpu/x86/smm.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/broadwell.h> #include <stdint.h>
diff --git a/src/northbridge/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c index db15dbb..7a93b9a 100644 --- a/src/northbridge/intel/broadwell/minihd.c +++ b/src/northbridge/intel/broadwell/minihd.c @@ -7,7 +7,7 @@ #include <device/pci_ops.h> #include <device/mmio.h> #include <soc/intel/common/hda_verb.h> -#include <soc/ramstage.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/igd.h>
static const u32 minihd_verb_table[] = { diff --git a/src/northbridge/intel/broadwell/pei_data.c b/src/northbridge/intel/broadwell/pei_data.c index 41fc475..56166eb 100644 --- a/src/northbridge/intel/broadwell/pei_data.c +++ b/src/northbridge/intel/broadwell/pei_data.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <console/streams.h> -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h>
diff --git a/src/northbridge/intel/broadwell/raminit.c b/src/northbridge/intel/broadwell/raminit.c index dca56b6..d40c2a3 100644 --- a/src/northbridge/intel/broadwell/raminit.c +++ b/src/northbridge/intel/broadwell/raminit.c @@ -14,10 +14,10 @@ #include <ec/google/chromeec/ec_commands.h> #endif #include <vendorcode/google/chromeos/chromeos.h> -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h>
diff --git a/src/northbridge/intel/broadwell/refcode.c b/src/northbridge/intel/broadwell/refcode.c index 5ba43cd..13be8b6 100644 --- a/src/northbridge/intel/broadwell/refcode.c +++ b/src/northbridge/intel/broadwell/refcode.c @@ -11,8 +11,8 @@ #include <stage_cache.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> -#include <soc/pm.h> -#include <soc/ramstage.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/ramstage.h>
static pei_wrapper_entry_t load_refcode_from_cache(void) { diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c index 1012ce2..3ac4ece 100644 --- a/src/northbridge/intel/broadwell/report_platform.c +++ b/src/northbridge/intel/broadwell/report_platform.c @@ -7,8 +7,8 @@ #include <string.h> #include <cpu/x86/msr.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h>
diff --git a/src/northbridge/intel/broadwell/romstage.c b/src/northbridge/intel/broadwell/romstage.c index efc26d9..064c203 100644 --- a/src/northbridge/intel/broadwell/romstage.c +++ b/src/northbridge/intel/broadwell/romstage.c @@ -4,8 +4,8 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <reg_script.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h>
diff --git a/src/northbridge/intel/broadwell/systemagent.c b/src/northbridge/intel/broadwell/systemagent.c index 15110da..67d78cf 100644 --- a/src/northbridge/intel/broadwell/systemagent.c +++ b/src/northbridge/intel/broadwell/systemagent.c @@ -10,10 +10,10 @@ #include <device/pci_ids.h> #include <intelblocks/power_limit.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <soc/cpu.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> +#include <cpu/intel/broadwell/broadwell.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/broadwell.h>
u8 systemagent_revision(void) diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h deleted file mode 100644 index e69de29..0000000 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ /dev/null diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 8772a02..56dd799 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -1,56 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef _BROADWELL_NVS_H_ -#define _BROADWELL_NVS_H_ - -#include <commonlib/helpers.h> -#include <soc/device_nvs.h> -#include <vendorcode/google/chromeos/gnvs.h> - -typedef struct global_nvs_t { - /* Miscellaneous */ - u16 osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 prm0; /* 0x03 - SMI function call parameter */ - u8 prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 prm2; /* 0x06 - SCI function call parameter */ - u8 prm3; /* 0x07 - SCI function call parameter */ - u8 lckf; /* 0x08 - Global Lock function for EC */ - u8 prm4; /* 0x09 - Lock function parameter */ - u8 prm5; /* 0x0a - Lock function parameter */ - u8 pcnt; /* 0x0b - Processor Count */ - u8 ppcm; /* 0x0c - Max PPC State */ - u8 tmps; /* 0x0d - Temperature Sensor ID */ - u8 tlvl; /* 0x0e - Throttle Level Limit */ - u8 flvl; /* 0x0f - Current FAN Level */ - u8 tcrt; /* 0x10 - Critical Threshold */ - u8 tpsv; /* 0x11 - Passive Threshold */ - u8 tmax; /* 0x12 - CPU Tj_max */ - u8 s5u0; /* 0x13 - Enable USB in S5 */ - u8 s3u0; /* 0x14 - Enable USB in S3 */ - u8 s33g; /* 0x15 - Enable 3G in S3 */ - u8 lids; /* 0x16 - LID State */ - u8 pwrs; /* 0x17 - AC Power State */ - u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ - u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ - u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ - u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ - u8 unused1[132]; /* 0x30 - 0xb3 - unused */ - - u8 unused2[76]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; - - /* Device specific (0x1000) */ - device_nvs_t dev; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - -void acpi_create_gnvs(global_nvs_t *gnvs); - -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); - -#endif +#include <southbridge/intel/wildcatpoint/nvs.h> diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 5c93352..8b6d4f3 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -3,7 +3,7 @@ #ifndef _BROADWELL_SYSTEMAGENT_H_ #define _BROADWELL_SYSTEMAGENT_H_
-#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h>
#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x))
diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/southbridge/intel/wildcatpoint/acpi.h similarity index 91% rename from src/soc/intel/broadwell/include/soc/acpi.h rename to src/southbridge/intel/wildcatpoint/acpi.h index 66ad450..618b627 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/southbridge/intel/wildcatpoint/acpi.h @@ -4,7 +4,7 @@ #define _BROADWELL_ACPI_H_
#include <acpi/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/nvs.h>
/* P-state configuration */ #define PSS_MAX_ENTRIES 8 diff --git a/src/southbridge/intel/wildcatpoint/acpi/pch.asl b/src/southbridge/intel/wildcatpoint/acpi/pch.asl index 07db9f7..540d262 100644 --- a/src/southbridge/intel/wildcatpoint/acpi/pch.asl +++ b/src/southbridge/intel/wildcatpoint/acpi/pch.asl @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/iomap.h> - Scope () { // IO-Trap at 0x800. This is the ACPI->SMI communication interface. diff --git a/src/southbridge/intel/wildcatpoint/adsp.c b/src/southbridge/intel/wildcatpoint/adsp.c index b8699a2..925b1b7 100644 --- a/src/southbridge/intel/wildcatpoint/adsp.c +++ b/src/southbridge/intel/wildcatpoint/adsp.c @@ -7,14 +7,14 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <soc/adsp.h> -#include <soc/device_nvs.h> -#include <soc/iobp.h> -#include <soc/nvs.h> -#include <soc/pch.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/adsp.h> +#include <southbridge/intel/wildcatpoint/device_nvs.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h>
static void adsp_init(struct device *dev) { diff --git a/src/soc/intel/broadwell/include/soc/adsp.h b/src/southbridge/intel/wildcatpoint/adsp.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/adsp.h rename to src/southbridge/intel/wildcatpoint/adsp.h diff --git a/src/southbridge/intel/wildcatpoint/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c index 61af770..572ea09 100644 --- a/src/southbridge/intel/wildcatpoint/bootblock.c +++ b/src/southbridge/intel/wildcatpoint/bootblock.c @@ -2,13 +2,13 @@
#include <arch/bootblock.h> #include <device/pci_ops.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/rcba.h> -#include <soc/spi.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/spi.h> #include <reg_script.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h>
/* diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/southbridge/intel/wildcatpoint/device_nvs.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/device_nvs.h rename to src/southbridge/intel/wildcatpoint/device_nvs.h diff --git a/src/southbridge/intel/wildcatpoint/early_pch.c b/src/southbridge/intel/wildcatpoint/early_pch.c index 9b73760..e8cb8aa 100644 --- a/src/southbridge/intel/wildcatpoint/early_pch.c +++ b/src/southbridge/intel/wildcatpoint/early_pch.c @@ -5,15 +5,15 @@ #include <device/pci_ops.h> #include <device/smbus_host.h> #include <reg_script.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/rcba.h> #include <northbridge/intel/broadwell/romstage.h> -#include <soc/smbus.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/smbus.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h>
const struct reg_script pch_interrupt_init_script[] = { /* diff --git a/src/southbridge/intel/wildcatpoint/early_smbus.c b/src/southbridge/intel/wildcatpoint/early_smbus.c index 5da5f4e..6f4d226 100644 --- a/src/southbridge/intel/wildcatpoint/early_smbus.c +++ b/src/southbridge/intel/wildcatpoint/early_smbus.c @@ -3,9 +3,9 @@ #include <device/pci_def.h> #include <device/smbus_host.h> #include <reg_script.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/smbus.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/smbus.h> #include <northbridge/intel/broadwell/romstage.h>
static const struct reg_script smbus_init_script[] = { diff --git a/src/southbridge/intel/wildcatpoint/ehci.c b/src/southbridge/intel/wildcatpoint/ehci.c index 5b977dd..81ad62d 100644 --- a/src/southbridge/intel/wildcatpoint/ehci.c +++ b/src/southbridge/intel/wildcatpoint/ehci.c @@ -5,8 +5,8 @@ #include <device/pci_ids.h> #include <device/pci_ehci.h> #include <device/pci_ops.h> -#include <soc/ehci.h> -#include <soc/pch.h> +#include <southbridge/intel/wildcatpoint/ehci.h> +#include <southbridge/intel/wildcatpoint/pch.h>
static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) diff --git a/src/soc/intel/broadwell/include/soc/ehci.h b/src/southbridge/intel/wildcatpoint/ehci.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/ehci.h rename to src/southbridge/intel/wildcatpoint/ehci.h diff --git a/src/southbridge/intel/wildcatpoint/elog.c b/src/southbridge/intel/wildcatpoint/elog.c index f918958..6e39cd0 100644 --- a/src/southbridge/intel/wildcatpoint/elog.c +++ b/src/southbridge/intel/wildcatpoint/elog.c @@ -5,8 +5,8 @@ #include <console/console.h> #include <stdint.h> #include <elog.h> -#include <soc/lpc.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pm.h>
static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { diff --git a/src/southbridge/intel/wildcatpoint/gpio.c b/src/southbridge/intel/wildcatpoint/gpio.c index ff1f019..62a7335 100644 --- a/src/southbridge/intel/wildcatpoint/gpio.c +++ b/src/southbridge/intel/wildcatpoint/gpio.c @@ -4,9 +4,9 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pm.h>
/* * This function will return a number that indicates which PIRQ diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/southbridge/intel/wildcatpoint/gpio.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/gpio.h rename to src/southbridge/intel/wildcatpoint/gpio.h diff --git a/src/southbridge/intel/wildcatpoint/hda.c b/src/southbridge/intel/wildcatpoint/hda.c index 1640825..0dbe6cd 100644 --- a/src/southbridge/intel/wildcatpoint/hda.c +++ b/src/southbridge/intel/wildcatpoint/hda.c @@ -8,9 +8,9 @@ #include <device/pci_ops.h> #include <device/mmio.h> #include <soc/intel/common/hda_verb.h> -#include <soc/pch.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h>
static void codecs_init(u8 *base, u32 codec_mask) { diff --git a/src/southbridge/intel/wildcatpoint/iobp.c b/src/southbridge/intel/wildcatpoint/iobp.c index 76a3e58..3332e26 100644 --- a/src/southbridge/intel/wildcatpoint/iobp.c +++ b/src/southbridge/intel/wildcatpoint/iobp.c @@ -2,8 +2,8 @@
#include <console/console.h> #include <delay.h> -#include <soc/iobp.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/rcba.h>
#define IOBP_RETRY 1000
diff --git a/src/soc/intel/broadwell/include/soc/iobp.h b/src/southbridge/intel/wildcatpoint/iobp.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/iobp.h rename to src/southbridge/intel/wildcatpoint/iobp.h diff --git a/src/soc/intel/broadwell/include/soc/iomap.h b/src/southbridge/intel/wildcatpoint/iomap.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/iomap.h rename to src/southbridge/intel/wildcatpoint/iomap.h diff --git a/src/southbridge/intel/wildcatpoint/lpc.c b/src/southbridge/intel/wildcatpoint/lpc.c index 5cfeb5f..b7f1fe3 100644 --- a/src/southbridge/intel/wildcatpoint/lpc.c +++ b/src/southbridge/intel/wildcatpoint/lpc.c @@ -15,17 +15,17 @@ #include <cbmem.h> #include <reg_script.h> #include <string.h> -#include <soc/gpio.h> -#include <soc/iobp.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/nvs.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <acpi/acpigen.h> #include <southbridge/intel/common/rtc.h>
diff --git a/src/soc/intel/broadwell/include/soc/lpc.h b/src/southbridge/intel/wildcatpoint/lpc.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/lpc.h rename to src/southbridge/intel/wildcatpoint/lpc.h diff --git a/src/southbridge/intel/wildcatpoint/me.c b/src/southbridge/intel/wildcatpoint/me.c index 7449902..3b1998e 100644 --- a/src/southbridge/intel/wildcatpoint/me.c +++ b/src/southbridge/intel/wildcatpoint/me.c @@ -20,13 +20,13 @@ #include <string.h> #include <delay.h> #include <elog.h> -#include <soc/me.h> -#include <soc/lpc.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/me.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h>
#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/southbridge/intel/wildcatpoint/me.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/me.h rename to src/southbridge/intel/wildcatpoint/me.h diff --git a/src/southbridge/intel/wildcatpoint/me_status.c b/src/southbridge/intel/wildcatpoint/me_status.c index 11b21ac..d11b26c 100644 --- a/src/southbridge/intel/wildcatpoint/me_status.c +++ b/src/southbridge/intel/wildcatpoint/me_status.c @@ -4,8 +4,8 @@ #include <console/console.h> #include <device/pci.h> #include <string.h> -#include <soc/pci_devs.h> -#include <soc/me.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/me.h> #include <delay.h>
#define ARRAY_TO_ELEMENT(__array__, __index__, __default__) \ diff --git a/src/southbridge/intel/wildcatpoint/nvs.h b/src/southbridge/intel/wildcatpoint/nvs.h new file mode 100644 index 0000000..b5fca62 --- /dev/null +++ b/src/southbridge/intel/wildcatpoint/nvs.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BROADWELL_NVS_H_ +#define _BROADWELL_NVS_H_ + +#include <commonlib/helpers.h> +#include <southbridge/intel/wildcatpoint/device_nvs.h> +#include <vendorcode/google/chromeos/gnvs.h> + +typedef struct global_nvs_t { + /* Miscellaneous */ + u16 osys; /* 0x00 - Operating System */ + u8 smif; /* 0x02 - SMI function call ("TRAP") */ + u8 prm0; /* 0x03 - SMI function call parameter */ + u8 prm1; /* 0x04 - SMI function call parameter */ + u8 scif; /* 0x05 - SCI function call (via _L00) */ + u8 prm2; /* 0x06 - SCI function call parameter */ + u8 prm3; /* 0x07 - SCI function call parameter */ + u8 lckf; /* 0x08 - Global Lock function for EC */ + u8 prm4; /* 0x09 - Lock function parameter */ + u8 prm5; /* 0x0a - Lock function parameter */ + u8 pcnt; /* 0x0b - Processor Count */ + u8 ppcm; /* 0x0c - Max PPC State */ + u8 tmps; /* 0x0d - Temperature Sensor ID */ + u8 tlvl; /* 0x0e - Throttle Level Limit */ + u8 flvl; /* 0x0f - Current FAN Level */ + u8 tcrt; /* 0x10 - Critical Threshold */ + u8 tpsv; /* 0x11 - Passive Threshold */ + u8 tmax; /* 0x12 - CPU Tj_max */ + u8 s5u0; /* 0x13 - Enable USB in S5 */ + u8 s3u0; /* 0x14 - Enable USB in S3 */ + u8 s33g; /* 0x15 - Enable 3G in S3 */ + u8 lids; /* 0x16 - LID State */ + u8 pwrs; /* 0x17 - AC Power State */ + u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ + u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ + u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ + u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ + u8 unused1[132]; /* 0x30 - 0xb3 - unused */ + + u8 unused2[76]; + + /* ChromeOS specific (0x100 - 0xfff) */ + chromeos_acpi_t chromeos; + + /* Device specific (0x1000) */ + device_nvs_t dev; +} __packed global_nvs_t; +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + +void acpi_create_gnvs(global_nvs_t *gnvs); + +/* Used in SMM to find the ACPI GNVS address */ +global_nvs_t *smm_get_gnvs(void); + +#endif diff --git a/src/southbridge/intel/wildcatpoint/pch.c b/src/southbridge/intel/wildcatpoint/pch.c index 479323d..1ac2967 100644 --- a/src/southbridge/intel/wildcatpoint/pch.c +++ b/src/southbridge/intel/wildcatpoint/pch.c @@ -5,13 +5,13 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> -#include <soc/iobp.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/serialio.h> -#include <soc/spi.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/serialio.h> +#include <southbridge/intel/wildcatpoint/spi.h>
u8 pch_revision(void) { diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/southbridge/intel/wildcatpoint/pch.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/pch.h rename to src/southbridge/intel/wildcatpoint/pch.h diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/southbridge/intel/wildcatpoint/pci_devs.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/pci_devs.h rename to src/southbridge/intel/wildcatpoint/pci_devs.h diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c index 2ec714f..4515ffb 100644 --- a/src/southbridge/intel/wildcatpoint/pcie.c +++ b/src/southbridge/intel/wildcatpoint/pcie.c @@ -7,13 +7,13 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <soc/gpio.h> -#include <soc/lpc.h> -#include <soc/iobp.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <cpu/intel/broadwell/broadwell.h> #include <delay.h>
diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/southbridge/intel/wildcatpoint/pm.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/pm.h rename to src/southbridge/intel/wildcatpoint/pm.h diff --git a/src/southbridge/intel/wildcatpoint/pmutil.c b/src/southbridge/intel/wildcatpoint/pmutil.c index 502a046..b66fb87 100644 --- a/src/southbridge/intel/wildcatpoint/pmutil.c +++ b/src/southbridge/intel/wildcatpoint/pmutil.c @@ -13,11 +13,11 @@ #include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <security/vboot/vbnv.h>
/* Print status bits with descriptive names */ diff --git a/src/southbridge/intel/wildcatpoint/power_state.c b/src/southbridge/intel/wildcatpoint/power_state.c index b9263b4..8522caa 100644 --- a/src/southbridge/intel/wildcatpoint/power_state.c +++ b/src/southbridge/intel/wildcatpoint/power_state.c @@ -9,10 +9,10 @@ #include <device/pci_def.h> #include <reg_script.h> #include <string.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h>
static struct chipset_power_state power_state; diff --git a/src/southbridge/intel/wildcatpoint/ramstage.c b/src/southbridge/intel/wildcatpoint/ramstage.c index 39550b7..8859261 100644 --- a/src/southbridge/intel/wildcatpoint/ramstage.c +++ b/src/southbridge/intel/wildcatpoint/ramstage.c @@ -4,10 +4,10 @@ #include <cbmem.h> #include <device/device.h> #include <string.h> -#include <soc/nvs.h> -#include <soc/pm.h> -#include <soc/ramstage.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <soc/intel/common/acpi.h> #include <assert.h>
diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/southbridge/intel/wildcatpoint/ramstage.h similarity index 89% rename from src/soc/intel/broadwell/include/soc/ramstage.h rename to src/southbridge/intel/wildcatpoint/ramstage.h index 18a23e1..b50cd19 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/southbridge/intel/wildcatpoint/ramstage.h @@ -4,7 +4,7 @@ #define _BROADWELL_RAMSTAGE_H_
#include <device/device.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h>
void broadwell_init_pre_device(void *chip_info); void broadwell_init_cpus(struct device *dev); diff --git a/src/soc/intel/broadwell/include/soc/rcba.h b/src/southbridge/intel/wildcatpoint/rcba.h similarity index 98% rename from src/soc/intel/broadwell/include/soc/rcba.h rename to src/southbridge/intel/wildcatpoint/rcba.h index 3bacb9d..9d06992 100644 --- a/src/soc/intel/broadwell/include/soc/rcba.h +++ b/src/southbridge/intel/wildcatpoint/rcba.h @@ -3,7 +3,7 @@ #ifndef _BROADWELL_RCBA_H_ #define _BROADWELL_RCBA_H_
-#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h>
#define RCBA8(x) *((volatile u8 *)(RCBA_BASE_ADDRESS + x)) #define RCBA16(x) *((volatile u16 *)(RCBA_BASE_ADDRESS + x)) diff --git a/src/southbridge/intel/wildcatpoint/sata.c b/src/southbridge/intel/wildcatpoint/sata.c index 5ddccc5..502d586 100644 --- a/src/southbridge/intel/wildcatpoint/sata.c +++ b/src/southbridge/intel/wildcatpoint/sata.c @@ -7,11 +7,11 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> -#include <soc/iobp.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/sata.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/sata.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h>
static inline u32 sir_read(struct device *dev, int idx) { diff --git a/src/soc/intel/broadwell/include/soc/sata.h b/src/southbridge/intel/wildcatpoint/sata.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/sata.h rename to src/southbridge/intel/wildcatpoint/sata.h diff --git a/src/southbridge/intel/wildcatpoint/serialio.c b/src/southbridge/intel/wildcatpoint/serialio.c index 20a5d9a..3dbbc6e 100644 --- a/src/southbridge/intel/wildcatpoint/serialio.c +++ b/src/southbridge/intel/wildcatpoint/serialio.c @@ -7,14 +7,14 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/iobp.h> -#include <soc/nvs.h> -#include <soc/pci_devs.h> -#include <soc/pch.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/serialio.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/serialio.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h>
/* Set D3Hot Power State in ACPI mode */ static void serialio_enable_d3hot(struct resource *res) diff --git a/src/soc/intel/broadwell/include/soc/serialio.h b/src/southbridge/intel/wildcatpoint/serialio.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/serialio.h rename to src/southbridge/intel/wildcatpoint/serialio.h diff --git a/src/southbridge/intel/wildcatpoint/smbus.c b/src/southbridge/intel/wildcatpoint/smbus.c index 562db4e..b8177e5 100644 --- a/src/southbridge/intel/wildcatpoint/smbus.c +++ b/src/southbridge/intel/wildcatpoint/smbus.c @@ -7,9 +7,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <soc/iomap.h> -#include <soc/ramstage.h> -#include <soc/smbus.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/smbus.h> #include <device/smbus_host.h>
static void pch_smbus_init(struct device *dev) diff --git a/src/soc/intel/broadwell/include/soc/smbus.h b/src/southbridge/intel/wildcatpoint/smbus.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/smbus.h rename to src/southbridge/intel/wildcatpoint/smbus.h diff --git a/src/southbridge/intel/wildcatpoint/smi.c b/src/southbridge/intel/wildcatpoint/smi.c index 1d3860a..1dc8b59 100644 --- a/src/southbridge/intel/wildcatpoint/smi.c +++ b/src/southbridge/intel/wildcatpoint/smi.c @@ -6,9 +6,9 @@ #include <arch/io.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> -#include <soc/iomap.h> -#include <soc/pch.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pm.h>
void smm_southbridge_clear_state(void) { diff --git a/src/southbridge/intel/wildcatpoint/smihandler.c b/src/southbridge/intel/wildcatpoint/smihandler.c index 85d6ae0..98e26ca 100644 --- a/src/southbridge/intel/wildcatpoint/smihandler.c +++ b/src/southbridge/intel/wildcatpoint/smihandler.c @@ -14,12 +14,12 @@ #include <elog.h> #include <halt.h> #include <option.h> -#include <soc/lpc.h> -#include <soc/nvs.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/rcba.h> -#include <soc/xhci.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/xhci.h> #include <drivers/intel/gma/i915_reg.h> #include <smmstore.h>
diff --git a/src/soc/intel/broadwell/include/soc/soc_chip.h b/src/southbridge/intel/wildcatpoint/soc_chip.h similarity index 80% rename from src/soc/intel/broadwell/include/soc/soc_chip.h rename to src/southbridge/intel/wildcatpoint/soc_chip.h index bbd556e..c59f562 100644 --- a/src/soc/intel/broadwell/include/soc/soc_chip.h +++ b/src/southbridge/intel/wildcatpoint/soc_chip.h @@ -3,6 +3,6 @@ #ifndef _SOC_BROADWELL_SOC_CHIP_H_ #define _SOC_BROADWELL_SOC_CHIP_H_
-#include "../../chip.h" +#include <soc/intel/broadwell/chip.h>
#endif /* _SOC_BROADWELL_SOC_CHIP_H_ */ diff --git a/src/soc/intel/broadwell/include/soc/spi.h b/src/southbridge/intel/wildcatpoint/spi.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/spi.h rename to src/southbridge/intel/wildcatpoint/spi.h diff --git a/src/southbridge/intel/wildcatpoint/uart.c b/src/southbridge/intel/wildcatpoint/uart.c index 6b0da2d..8d3e7a7 100644 --- a/src/southbridge/intel/wildcatpoint/uart.c +++ b/src/southbridge/intel/wildcatpoint/uart.c @@ -4,8 +4,8 @@ #include <reg_script.h> #include <stdint.h> #include <uart8250.h> -#include <soc/iobp.h> -#include <soc/serialio.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/serialio.h>
const struct reg_script uart_init[] = { /* Set MMIO BAR */ diff --git a/src/southbridge/intel/wildcatpoint/xhci.c b/src/southbridge/intel/wildcatpoint/xhci.c index 7541fef..cef2bed 100644 --- a/src/southbridge/intel/wildcatpoint/xhci.c +++ b/src/southbridge/intel/wildcatpoint/xhci.c @@ -7,8 +7,8 @@ #include <acpi/acpi.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <soc/ramstage.h> -#include <soc/xhci.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/xhci.h> #include <cpu/intel/broadwell/broadwell.h>
#ifdef __SIMPLE_DEVICE__ diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/southbridge/intel/wildcatpoint/xhci.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/xhci.h rename to src/southbridge/intel/wildcatpoint/xhci.h
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41938
to look at the new patch set (#5).
Change subject: southbridge/intel/wildcatpoint: Add header files ......................................................................
southbridge/intel/wildcatpoint: Add header files
Relocate southbridge-related headers from soc to the southbridge scope. Note that the code in soc/intel/common expects to find `soc/nvs.h`.
And yes, some prototypes are now in the wrong place. This will be fixed in the next commits, once the soc/intel/broadwell subfolder is no more.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: If2bdef9b44ec8c93c1469074dc51a9964b4101ce Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/cpu.c M src/cpu/intel/broadwell/romstage.c M src/cpu/intel/broadwell/smmrelocate.c M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/auron/variants/auron_paine/gpio.c M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/gpio.c M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/gpio.c M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/gpio.c M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/gpio.c M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/gpio.c M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/jecht/variants/guado/gpio.c M src/mainboard/google/jecht/variants/guado/pei_data.c M src/mainboard/google/jecht/variants/jecht/gpio.c M src/mainboard/google/jecht/variants/jecht/pei_data.c M src/mainboard/google/jecht/variants/rikku/gpio.c M src/mainboard/google/jecht/variants/rikku/pei_data.c M src/mainboard/google/jecht/variants/tidus/gpio.c M src/mainboard/google/jecht/variants/tidus/pei_data.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/intel/wtm2/gpio.c M src/mainboard/intel/wtm2/pei_data.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/mainboard/purism/librem_bdw/gpio.c M src/northbridge/intel/broadwell/acpi/broadwell.asl M src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/finalize.c M src/northbridge/intel/broadwell/igd.c M src/northbridge/intel/broadwell/memmap.c M src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/pei_data.c M src/northbridge/intel/broadwell/raminit.c M src/northbridge/intel/broadwell/refcode.c M src/northbridge/intel/broadwell/report_platform.c M src/northbridge/intel/broadwell/romstage.c M src/northbridge/intel/broadwell/systemagent.c D src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/systemagent.h R src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/acpi/pch.asl M src/southbridge/intel/wildcatpoint/adsp.c R src/southbridge/intel/wildcatpoint/adsp.h M src/southbridge/intel/wildcatpoint/bootblock.c R src/southbridge/intel/wildcatpoint/device_nvs.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/ehci.c R src/southbridge/intel/wildcatpoint/ehci.h M src/southbridge/intel/wildcatpoint/elog.c M src/southbridge/intel/wildcatpoint/gpio.c R src/southbridge/intel/wildcatpoint/gpio.h M src/southbridge/intel/wildcatpoint/hda.c M src/southbridge/intel/wildcatpoint/iobp.c R src/southbridge/intel/wildcatpoint/iobp.h R src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/lpc.c R src/southbridge/intel/wildcatpoint/lpc.h M src/southbridge/intel/wildcatpoint/me.c R src/southbridge/intel/wildcatpoint/me.h M src/southbridge/intel/wildcatpoint/me_status.c A src/southbridge/intel/wildcatpoint/nvs.h M src/southbridge/intel/wildcatpoint/pch.c R src/southbridge/intel/wildcatpoint/pch.h R src/southbridge/intel/wildcatpoint/pci_devs.h M src/southbridge/intel/wildcatpoint/pcie.c R src/southbridge/intel/wildcatpoint/pm.h M src/southbridge/intel/wildcatpoint/pmutil.c M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c R src/southbridge/intel/wildcatpoint/ramstage.h R src/southbridge/intel/wildcatpoint/rcba.h M src/southbridge/intel/wildcatpoint/sata.c R src/southbridge/intel/wildcatpoint/sata.h M src/southbridge/intel/wildcatpoint/serialio.c R src/southbridge/intel/wildcatpoint/serialio.h M src/southbridge/intel/wildcatpoint/smbus.c R src/southbridge/intel/wildcatpoint/smbus.h M src/southbridge/intel/wildcatpoint/smi.c M src/southbridge/intel/wildcatpoint/smihandler.c R src/southbridge/intel/wildcatpoint/soc_chip.h R src/southbridge/intel/wildcatpoint/spi.h M src/southbridge/intel/wildcatpoint/uart.c M src/southbridge/intel/wildcatpoint/xhci.c R src/southbridge/intel/wildcatpoint/xhci.h 111 files changed, 276 insertions(+), 275 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/41938/5
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41938
to look at the new patch set (#9).
Change subject: southbridge/intel/wildcatpoint: Add header files ......................................................................
southbridge/intel/wildcatpoint: Add header files
Relocate southbridge-related headers from soc to the southbridge scope. Note that the code in soc/intel/common expects to find `soc/nvs.h`.
And yes, some prototypes are now in the wrong place. This will be fixed in the next commits, once the soc/intel/broadwell subfolder is no more.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: If2bdef9b44ec8c93c1469074dc51a9964b4101ce Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/cpu.c M src/cpu/intel/broadwell/romstage.c M src/cpu/intel/broadwell/smmrelocate.c M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/auron/variants/auron_paine/gpio.c M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/gpio.c M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/gpio.c M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/gpio.c M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/gpio.c M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/gpio.c M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/jecht/variants/guado/gpio.c M src/mainboard/google/jecht/variants/guado/pei_data.c M src/mainboard/google/jecht/variants/jecht/gpio.c M src/mainboard/google/jecht/variants/jecht/pei_data.c M src/mainboard/google/jecht/variants/rikku/gpio.c M src/mainboard/google/jecht/variants/rikku/pei_data.c M src/mainboard/google/jecht/variants/tidus/gpio.c M src/mainboard/google/jecht/variants/tidus/pei_data.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/intel/wtm2/gpio.c M src/mainboard/intel/wtm2/pei_data.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/mainboard/purism/librem_bdw/gpio.c M src/northbridge/intel/broadwell/acpi/broadwell.asl M src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/finalize.c M src/northbridge/intel/broadwell/igd.c M src/northbridge/intel/broadwell/memmap.c M src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/pei_data.c M src/northbridge/intel/broadwell/raminit.c M src/northbridge/intel/broadwell/refcode.c M src/northbridge/intel/broadwell/report_platform.c M src/northbridge/intel/broadwell/romstage.c M src/northbridge/intel/broadwell/systemagent.c D src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/systemagent.h R src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/acpi/pch.asl M src/southbridge/intel/wildcatpoint/adsp.c R src/southbridge/intel/wildcatpoint/adsp.h M src/southbridge/intel/wildcatpoint/bootblock.c R src/southbridge/intel/wildcatpoint/device_nvs.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/ehci.c R src/southbridge/intel/wildcatpoint/ehci.h M src/southbridge/intel/wildcatpoint/elog.c M src/southbridge/intel/wildcatpoint/gpio.c R src/southbridge/intel/wildcatpoint/gpio.h M src/southbridge/intel/wildcatpoint/hda.c M src/southbridge/intel/wildcatpoint/iobp.c R src/southbridge/intel/wildcatpoint/iobp.h R src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/lpc.c R src/southbridge/intel/wildcatpoint/lpc.h M src/southbridge/intel/wildcatpoint/me.c R src/southbridge/intel/wildcatpoint/me.h M src/southbridge/intel/wildcatpoint/me_status.c A src/southbridge/intel/wildcatpoint/nvs.h M src/southbridge/intel/wildcatpoint/pch.c R src/southbridge/intel/wildcatpoint/pch.h R src/southbridge/intel/wildcatpoint/pci_devs.h M src/southbridge/intel/wildcatpoint/pcie.c R src/southbridge/intel/wildcatpoint/pm.h M src/southbridge/intel/wildcatpoint/pmutil.c M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c R src/southbridge/intel/wildcatpoint/ramstage.h R src/southbridge/intel/wildcatpoint/rcba.h M src/southbridge/intel/wildcatpoint/sata.c R src/southbridge/intel/wildcatpoint/sata.h M src/southbridge/intel/wildcatpoint/serialio.c R src/southbridge/intel/wildcatpoint/serialio.h M src/southbridge/intel/wildcatpoint/smbus.c R src/southbridge/intel/wildcatpoint/smbus.h M src/southbridge/intel/wildcatpoint/smi.c M src/southbridge/intel/wildcatpoint/smihandler.c R src/southbridge/intel/wildcatpoint/soc_chip.h R src/southbridge/intel/wildcatpoint/spi.h M src/southbridge/intel/wildcatpoint/uart.c M src/southbridge/intel/wildcatpoint/xhci.c R src/southbridge/intel/wildcatpoint/xhci.h 111 files changed, 276 insertions(+), 275 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/41938/9
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41938
to look at the new patch set (#12).
Change subject: southbridge/intel/wildcatpoint: Add header files ......................................................................
southbridge/intel/wildcatpoint: Add header files
Relocate southbridge-related headers from soc to the southbridge scope. Note that the code in soc/intel/common expects to find `soc/nvs.h`.
And yes, some prototypes are now in the wrong place. This will be fixed in the next commits, once the soc/intel/broadwell subfolder is no more.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: If2bdef9b44ec8c93c1469074dc51a9964b4101ce Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/cpu.c M src/cpu/intel/broadwell/romstage.c M src/cpu/intel/broadwell/smmrelocate.c M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/auron/variants/auron_paine/gpio.c M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/gpio.c M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/gpio.c M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/gpio.c M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/gpio.c M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/gpio.c M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/jecht/variants/guado/gpio.c M src/mainboard/google/jecht/variants/guado/pei_data.c M src/mainboard/google/jecht/variants/jecht/gpio.c M src/mainboard/google/jecht/variants/jecht/pei_data.c M src/mainboard/google/jecht/variants/rikku/gpio.c M src/mainboard/google/jecht/variants/rikku/pei_data.c M src/mainboard/google/jecht/variants/tidus/gpio.c M src/mainboard/google/jecht/variants/tidus/pei_data.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/intel/wtm2/gpio.c M src/mainboard/intel/wtm2/pei_data.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/mainboard/purism/librem_bdw/gpio.c M src/northbridge/intel/broadwell/acpi/broadwell.asl M src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/finalize.c M src/northbridge/intel/broadwell/igd.c M src/northbridge/intel/broadwell/memmap.c M src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/pei_data.c M src/northbridge/intel/broadwell/raminit.c M src/northbridge/intel/broadwell/refcode.c M src/northbridge/intel/broadwell/report_platform.c M src/northbridge/intel/broadwell/romstage.c M src/northbridge/intel/broadwell/systemagent.c D src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/systemagent.h R src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/acpi/pch.asl M src/southbridge/intel/wildcatpoint/adsp.c R src/southbridge/intel/wildcatpoint/adsp.h M src/southbridge/intel/wildcatpoint/bootblock.c R src/southbridge/intel/wildcatpoint/device_nvs.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/ehci.c R src/southbridge/intel/wildcatpoint/ehci.h M src/southbridge/intel/wildcatpoint/elog.c M src/southbridge/intel/wildcatpoint/gpio.c R src/southbridge/intel/wildcatpoint/gpio.h M src/southbridge/intel/wildcatpoint/hda.c M src/southbridge/intel/wildcatpoint/iobp.c R src/southbridge/intel/wildcatpoint/iobp.h R src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/lpc.c R src/southbridge/intel/wildcatpoint/lpc.h M src/southbridge/intel/wildcatpoint/me.c R src/southbridge/intel/wildcatpoint/me.h M src/southbridge/intel/wildcatpoint/me_status.c A src/southbridge/intel/wildcatpoint/nvs.h M src/southbridge/intel/wildcatpoint/pch.c R src/southbridge/intel/wildcatpoint/pch.h R src/southbridge/intel/wildcatpoint/pci_devs.h M src/southbridge/intel/wildcatpoint/pcie.c R src/southbridge/intel/wildcatpoint/pm.h M src/southbridge/intel/wildcatpoint/pmutil.c M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c R src/southbridge/intel/wildcatpoint/ramstage.h R src/southbridge/intel/wildcatpoint/rcba.h M src/southbridge/intel/wildcatpoint/sata.c R src/southbridge/intel/wildcatpoint/sata.h M src/southbridge/intel/wildcatpoint/serialio.c R src/southbridge/intel/wildcatpoint/serialio.h M src/southbridge/intel/wildcatpoint/smbus.c R src/southbridge/intel/wildcatpoint/smbus.h M src/southbridge/intel/wildcatpoint/smi.c M src/southbridge/intel/wildcatpoint/smihandler.c R src/southbridge/intel/wildcatpoint/soc_chip.h R src/southbridge/intel/wildcatpoint/spi.h M src/southbridge/intel/wildcatpoint/uart.c M src/southbridge/intel/wildcatpoint/xhci.c R src/southbridge/intel/wildcatpoint/xhci.h 111 files changed, 276 insertions(+), 275 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/41938/12
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41938
to look at the new patch set (#16).
Change subject: southbridge/intel/wildcatpoint: Add header files ......................................................................
southbridge/intel/wildcatpoint: Add header files
Relocate southbridge-related headers from soc to the southbridge scope. Note that the code in soc/intel/common expects to find `soc/nvs.h`.
And yes, some prototypes are now in the wrong place. This will be fixed in the next commits, once the soc/intel/broadwell subfolder is no more.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: If2bdef9b44ec8c93c1469074dc51a9964b4101ce Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/cpu.c M src/cpu/intel/broadwell/romstage.c M src/cpu/intel/broadwell/smmrelocate.c M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/auron/variants/auron_paine/gpio.c M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/gpio.c M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/gpio.c M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/gpio.c M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/gpio.c M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/gpio.c M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/jecht/variants/guado/gpio.c M src/mainboard/google/jecht/variants/guado/pei_data.c M src/mainboard/google/jecht/variants/jecht/gpio.c M src/mainboard/google/jecht/variants/jecht/pei_data.c M src/mainboard/google/jecht/variants/rikku/gpio.c M src/mainboard/google/jecht/variants/rikku/pei_data.c M src/mainboard/google/jecht/variants/tidus/gpio.c M src/mainboard/google/jecht/variants/tidus/pei_data.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/intel/wtm2/gpio.c M src/mainboard/intel/wtm2/pei_data.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/mainboard/purism/librem_bdw/gpio.c M src/northbridge/intel/broadwell/acpi/broadwell.asl M src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/finalize.c M src/northbridge/intel/broadwell/igd.c M src/northbridge/intel/broadwell/memmap.c M src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/pei_data.c M src/northbridge/intel/broadwell/raminit.c M src/northbridge/intel/broadwell/refcode.c M src/northbridge/intel/broadwell/report_platform.c M src/northbridge/intel/broadwell/romstage.c M src/northbridge/intel/broadwell/systemagent.c D src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/systemagent.h R src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/acpi/pch.asl M src/southbridge/intel/wildcatpoint/adsp.c R src/southbridge/intel/wildcatpoint/adsp.h M src/southbridge/intel/wildcatpoint/bootblock.c R src/southbridge/intel/wildcatpoint/device_nvs.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/ehci.c R src/southbridge/intel/wildcatpoint/ehci.h M src/southbridge/intel/wildcatpoint/elog.c M src/southbridge/intel/wildcatpoint/gpio.c R src/southbridge/intel/wildcatpoint/gpio.h M src/southbridge/intel/wildcatpoint/hda.c M src/southbridge/intel/wildcatpoint/iobp.c R src/southbridge/intel/wildcatpoint/iobp.h R src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/lpc.c R src/southbridge/intel/wildcatpoint/lpc.h M src/southbridge/intel/wildcatpoint/me.c R src/southbridge/intel/wildcatpoint/me.h M src/southbridge/intel/wildcatpoint/me_status.c A src/southbridge/intel/wildcatpoint/nvs.h M src/southbridge/intel/wildcatpoint/pch.c R src/southbridge/intel/wildcatpoint/pch.h R src/southbridge/intel/wildcatpoint/pci_devs.h M src/southbridge/intel/wildcatpoint/pcie.c R src/southbridge/intel/wildcatpoint/pm.h M src/southbridge/intel/wildcatpoint/pmutil.c M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c R src/southbridge/intel/wildcatpoint/ramstage.h R src/southbridge/intel/wildcatpoint/rcba.h M src/southbridge/intel/wildcatpoint/sata.c R src/southbridge/intel/wildcatpoint/sata.h M src/southbridge/intel/wildcatpoint/serialio.c R src/southbridge/intel/wildcatpoint/serialio.h M src/southbridge/intel/wildcatpoint/smbus.c R src/southbridge/intel/wildcatpoint/smbus.h M src/southbridge/intel/wildcatpoint/smi.c M src/southbridge/intel/wildcatpoint/smihandler.c R src/southbridge/intel/wildcatpoint/soc_chip.h R src/southbridge/intel/wildcatpoint/spi.h M src/southbridge/intel/wildcatpoint/uart.c M src/southbridge/intel/wildcatpoint/xhci.c R src/southbridge/intel/wildcatpoint/xhci.h 111 files changed, 272 insertions(+), 271 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/41938/16
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41938 )
Change subject: southbridge/intel/wildcatpoint: Add header files ......................................................................
Abandoned
-
Angel Pons (Code Review)