[S] Change in coreboot[main]: mb/google/fatcat: Add power limits for additional PTL-H variants

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86339?usp=email )

Change subject: mb/google/fatcat: Add power limits for additional PTL-H variants
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mb/google/fatcat: Add power limits for additional PTL-H variants

This commit adds power limit configurations for additional variants of
the Intel PTL-H platform found on Fatcat. Specifically, it adds entries
for PCI Device IDs 2, 3, and 4. These configurations define the PL1,
PL2, and PL4 power limits, as well as the associated CPU TDP and
power limits index.  The PL4 values are currently placeholders and
marked for future fine-tuning.

BUG=b:395130929
TEST=Able to boot google/fatcat with 65W USB-C PD charger.

Change-Id: I86befb07f39a5e292365ea40ea08d0f93f38a7a6
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
1 file changed, 30 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/86339/1

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
index 4b9cfd2..969cd4a 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
@@ -18,6 +18,36 @@
    	.pl2_max_power = 50000,
    	.pl4_power = 50000 /* TODO: needs fine tuning */
    },
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
+		.cpu_tdp = 25,
+		.power_limits_index = PTL_H_1_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 50000 /* TODO: needs fine tuning */
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
+		.cpu_tdp = 25,
+		.power_limits_index = PTL_H_2_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 50000 /* TODO: needs fine tuning */
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
+		.cpu_tdp = 25,
+		.power_limits_index = PTL_H_2_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 50000 /* TODO: needs fine tuning */
+	},
 };

void baseboard_devtree_update(void)