Change in coreboot[master]: [WIP]: soc/amd/cezanne: Generate PCI routing table - coreboot-gerrit

26 Apr 2021


      Attention is currently required from: Jason Glenesk, Marshall Dawson, Eric Peers, Karthik Ramasubramanian, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51556 )
Change subject: [WIP]: soc/amd/cezanne: Generate PCI routing table
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Patch Set 1:
(1 comment)
File src/soc/amd/cezanne/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/51556/comment/3b97dcf6_8db8b985 
PS1, Line 355:
...
Should we also populate the PIRQ data so that amd_pci_util driver can configure PCI_INT_LINE registe […]
Yeah, the picasso version of this file contains that.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326
Gerrit-Change-Number: 51556
Gerrit-PatchSet: 1
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Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de
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