Change in coreboot[master]: mb/google/asurada: Add a stub implementation of Asurada mainboard
CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add a stub implementation of Asurada mainboard ......................................................................
mb/google/asurada: Add a stub implementation of Asurada mainboard
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 --- A src/mainboard/google/asurada/Kconfig A src/mainboard/google/asurada/Kconfig.name A src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/bootblock.c A src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/chromeos.fmd A src/mainboard/google/asurada/devicetree.cb A src/mainboard/google/asurada/mainboard.c A src/mainboard/google/asurada/memlayout.ld A src/mainboard/google/asurada/reset.c 10 files changed, 199 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/43963/1
diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig new file mode 100644 index 0000000..aeb13b0 --- /dev/null +++ b/src/mainboard/google/asurada/Kconfig @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# Umbrella option to be selected by variant boards. +config BOARD_GOOGLE_ASURADA_COMMON + def_bool n + +if BOARD_GOOGLE_ASURADA_COMMON + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOOTBLOCK_CONSOLE + select SOC_MEDIATEK_MT8192 + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select SPI_FLASH + select SPI_FLASH_INCLUDE_ALL_DRIVERS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SPI + select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT + select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER + +config MAINBOARD_DIR + string + default "google/asurada" + +config MAINBOARD_PART_NUMBER + string + default "Asurada" if BOARD_GOOGLE_ASURADA + +config DRIVER_TPM_SPI_BUS + hex + default 0x0 + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 1 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x2 + +endif diff --git a/src/mainboard/google/asurada/Kconfig.name b/src/mainboard/google/asurada/Kconfig.name new file mode 100644 index 0000000..df3dc24 --- /dev/null +++ b/src/mainboard/google/asurada/Kconfig.name @@ -0,0 +1,5 @@ +comment "Asurada" + +config BOARD_GOOGLE_ASURADA + bool "-> Asurada" + select BOARD_GOOGLE_ASURADA_COMMON diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc new file mode 100644 index 0000000..80b7c0b --- /dev/null +++ b/src/mainboard/google/asurada/Makefile.inc @@ -0,0 +1,12 @@ +bootblock-y += memlayout.ld +bootblock-y += bootblock.c + +verstage-y += memlayout.ld +verstage-y += reset.c + +romstage-y += memlayout.ld + +ramstage-y += memlayout.ld +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c new file mode 100644 index 0000000..5dcae8c --- /dev/null +++ b/src/mainboard/google/asurada/bootblock.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c new file mode 100644 index 0000000..8f9fa53 --- /dev/null +++ b/src/mainboard/google/asurada/chromeos.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <security/tpm/tis.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +} + +int get_write_protect_state(void) +{ + return 0; +} + +int tis_plat_irq_status(void) +{ + return 0; +} diff --git a/src/mainboard/google/asurada/chromeos.fmd b/src/mainboard/google/asurada/chromeos.fmd new file mode 100644 index 0000000..2635854 --- /dev/null +++ b/src/mainboard/google/asurada/chromeos.fmd @@ -0,0 +1,45 @@ +# Firmware Layout Description for Chrome OS. +# +# The size and address of every section must be aligned to at least 4K, except: +# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. +# +# 'FMAP' may be found by binary search so its starting address should be better +# aligned to larger values. +# +# For sections to be preserved on update, add (PRESERVE) to individual sections +# instead of a group section; otherwise the preserved data may be wrong if you +# resize or reorder sections inside a group. + +FLASH@0x0 8M { + WP_RO@0x0 4M { + RO_SECTION { + BOOTBLOCK 128K + FMAP 4K + COREBOOT(CBFS) + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 32K # At least 16K. + } + RW_SECTION_A 1500K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + RW_MISC 36K { + RW_VPD(PRESERVE) 16K # At least 8K. + RW_NVRAM(PRESERVE) 8K + RW_DDR_TRAINING(PRESERVE) 8K + RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + } + RW_SECTION_B 1500K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 0x100 + } + RW_SHARED 36K { # Will be force updated on recovery. + SHARED_DATA 4K # 4K or less for netboot params. + RW_UNUSED + } + RW_LEGACY(CBFS) 1M # Minimal 1M. +} diff --git a/src/mainboard/google/asurada/devicetree.cb b/src/mainboard/google/asurada/devicetree.cb new file mode 100644 index 0000000..9f682c3 --- /dev/null +++ b/src/mainboard/google/asurada/devicetree.cb @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/mediatek/mt8192 + device cpu_cluster 0 on + device cpu 0 on end + end +end diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c new file mode 100644 index 0000000..e6040fa --- /dev/null +++ b/src/mainboard/google/asurada/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +static void mainboard_init(struct device *dev) +{ +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/asurada/memlayout.ld b/src/mainboard/google/asurada/memlayout.ld new file mode 100644 index 0000000..0f1fcec --- /dev/null +++ b/src/mainboard/google/asurada/memlayout.ld @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/asurada/reset.c b/src/mainboard/google/asurada/reset.c new file mode 100644 index 0000000..3a97ee5 --- /dev/null +++ b/src/mainboard/google/asurada/reset.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <reset.h> + +void do_board_reset(void) +{ +}
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add a stub implementation of Asurada mainboard ......................................................................
Patch Set 1:
No src/mainboard/google/asurada/board_info.txt found
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43963
to look at the new patch set (#2).
Change subject: mb/google/asurada: Add a stub implementation of Asurada mainboard ......................................................................
mb/google/asurada: Add a stub implementation of Asurada mainboard
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 --- A src/mainboard/google/asurada/Kconfig A src/mainboard/google/asurada/Kconfig.name A src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/board_info.txt A src/mainboard/google/asurada/bootblock.c A src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/chromeos.fmd A src/mainboard/google/asurada/devicetree.cb A src/mainboard/google/asurada/mainboard.c A src/mainboard/google/asurada/memlayout.ld A src/mainboard/google/asurada/reset.c 11 files changed, 205 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/43963/2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43963
to look at the new patch set (#3).
Change subject: mb/google/asurada: Add a stub implementation of Asurada mainboard ......................................................................
mb/google/asurada: Add a stub implementation of Asurada mainboard
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 --- A src/mainboard/google/asurada/Kconfig A src/mainboard/google/asurada/Kconfig.name A src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/board_info.txt A src/mainboard/google/asurada/bootblock.c A src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/chromeos.fmd A src/mainboard/google/asurada/devicetree.cb A src/mainboard/google/asurada/mainboard.c A src/mainboard/google/asurada/memlayout.ld A src/mainboard/google/asurada/reset.c 11 files changed, 205 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/43963/3
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43963
to look at the new patch set (#4).
Change subject: mb/google/asurada: Add a stub implementation of Asurada mainboard ......................................................................
mb/google/asurada: Add a stub implementation of Asurada mainboard
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 --- A src/mainboard/google/asurada/Kconfig A src/mainboard/google/asurada/Kconfig.name A src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/board_info.txt A src/mainboard/google/asurada/bootblock.c A src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/chromeos.fmd A src/mainboard/google/asurada/devicetree.cb A src/mainboard/google/asurada/mainboard.c A src/mainboard/google/asurada/memlayout.ld A src/mainboard/google/asurada/reset.c 11 files changed, 205 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/43963/4
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add a stub implementation of Asurada mainboard ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43963/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43963/6//COMMIT_MSG@7 PS6, Line 7: Add a stub implementation of Asurada mainboard mb/google/asurada: new MT8192 mainboard "Asurada"
The placeholder functions and build rules for generating a minimal firmware to run on MT8192 SOC based mainboard "Asurada".
https://review.coreboot.org/c/coreboot/+/43963/6/src/mainboard/google/asurad... File src/mainboard/google/asurada/chromeos.c:
https://review.coreboot.org/c/coreboot/+/43963/6/src/mainboard/google/asurad... PS6, Line 10: } can you add the placeholder for 'boardid.c' as well?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43963
to look at the new patch set (#7).
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
mb/google/asurada: Add new MT8192 mainboard "Asurada"
The placeholder functions and build rules for generating a minimal firmware to run on MT8192 SOC based mainboard "Asurada".
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 --- A src/mainboard/google/asurada/Kconfig A src/mainboard/google/asurada/Kconfig.name A src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/board_info.txt A src/mainboard/google/asurada/boardid.c A src/mainboard/google/asurada/bootblock.c A src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/chromeos.fmd A src/mainboard/google/asurada/devicetree.cb A src/mainboard/google/asurada/mainboard.c A src/mainboard/google/asurada/memlayout.ld A src/mainboard/google/asurada/reset.c 12 files changed, 222 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/43963/7
CK HU has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43963/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43963/6//COMMIT_MSG@7 PS6, Line 7: Add a stub implementation of Asurada mainboard
mb/google/asurada: new MT8192 mainboard "Asurada" […]
Done
https://review.coreboot.org/c/coreboot/+/43963/6/src/mainboard/google/asurad... File src/mainboard/google/asurada/chromeos.c:
https://review.coreboot.org/c/coreboot/+/43963/6/src/mainboard/google/asurad... PS6, Line 10: }
can you add the placeholder for 'boardid. […]
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 7: Code-Review+2
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 7: -Code-Review
build failure:
aarch64-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_ASURADA/ramstage/mainboard/google/asurada/static.o:(.data._dev0+0xa8): undefined reference to `soc_mediatek_mt8192_ops' aarch64-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_ASURADA/ramstage/mainboard/google/asurada/static.o:(.data._dev1+0xa8): undefined reference to `soc_mediatek_mt8192_ops'
CK HU has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 7:
Patch Set 7: -Code-Review
build failure:
aarch64-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_ASURADA/ramstage/mainboard/google/asurada/static.o:(.data._dev0+0xa8): undefined reference to `soc_mediatek_mt8192_ops' aarch64-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_ASURADA/ramstage/mainboard/google/asurada/static.o:(.data._dev1+0xa8): undefined reference to `soc_mediatek_mt8192_ops'
When I checkout to this patch, I does not find soc_mediatek_mt8192_ops in the whole source. Why this happen?
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 7:
When I checkout to this patch, I does not find soc_mediatek_mt8192_ops in the whole source. Why this happen?
It is an auto generated reference from util/sconfig. Please include that for src/soc/mediatek/mt8192/soc.c
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 7:
Patch Set 7:
Patch Set 7: -Code-Review
build failure:
aarch64-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_ASURADA/ramstage/mainboard/google/asurada/static.o:(.data._dev0+0xa8): undefined reference to `soc_mediatek_mt8192_ops' aarch64-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_ASURADA/ramstage/mainboard/google/asurada/static.o:(.data._dev1+0xa8): undefined reference to `soc_mediatek_mt8192_ops'
When I checkout to this patch, I does not find soc_mediatek_mt8192_ops in the whole source. Why this happen?
For MT8183 there's soc_mediatek_mt8183_ops defined in soc/mediatek/mt8183/soc.c. Do we need to add soc/mediatek/mt8192/soc.c?
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 7:
I think you need to pull in https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+... before landing this patch.
CK HU has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 7:
Patch Set 7:
I think you need to pull in https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+... before landing this patch.
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 8: Code-Review+2
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43963/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43963/8//COMMIT_MSG@9 PS8, Line 9: firmware Line exceeding 72 characters.
https://review.coreboot.org/c/coreboot/+/43963/8/src/mainboard/google/asurad... File src/mainboard/google/asurada/Kconfig:
https://review.coreboot.org/c/coreboot/+/43963/8/src/mainboard/google/asurad... PS8, Line 1: ## : ## This file is part of the coreboot project. : ## : ## : ## This program is free software; you can redistribute it and/or modify : ## it under the terms of the GNU General Public License as published by : ## the Free Software Foundation; version 2 of the License. : ## : ## This program is distributed in the hope that it will be useful, : ## but WITHOUT ANY WARRANTY; without even the implied warranty of : ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : ## GNU General Public License for more details. : ## Please use
## SPDX-License-Identifier: GPL-2.0-only
https://review.coreboot.org/c/coreboot/+/43963/8/src/mainboard/google/asurad... File src/mainboard/google/asurada/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43963/8/src/mainboard/google/asurad... PS8, Line 1: ## : ## This file is part of the coreboot project. : ## : ## : ## This program is free software; you can redistribute it and/or modify : ## it under the terms of the GNU General Public License as published by : ## the Free Software Foundation; version 2 of the License. : ## : ## This program is distributed in the hope that it will be useful, : ## but WITHOUT ANY WARRANTY; without even the implied warranty of : ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : ## GNU General Public License for more details. : ## Please use
## SPDX-License-Identifier: GPL-2.0-only
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 8: -Code-Review
Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43963
to look at the new patch set (#9).
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
mb/google/asurada: Add new MT8192 mainboard "Asurada"
The placeholder functions and build rules for generating a minimal firmware to run on MT8192 SOC based mainboard "Asurada".
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 --- A src/mainboard/google/asurada/Kconfig A src/mainboard/google/asurada/Kconfig.name A src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/board_info.txt A src/mainboard/google/asurada/boardid.c A src/mainboard/google/asurada/bootblock.c A src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/chromeos.fmd A src/mainboard/google/asurada/devicetree.cb A src/mainboard/google/asurada/mainboard.c A src/mainboard/google/asurada/memlayout.ld A src/mainboard/google/asurada/reset.c 12 files changed, 198 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/43963/9
Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43963
to look at the new patch set (#10).
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
mb/google/asurada: Add new MT8192 mainboard "Asurada"
The placeholder functions and build rules for generating a minimal firmware to run on MT8192 SOC based mainboard "Asurada".
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 --- A src/mainboard/google/asurada/Kconfig A src/mainboard/google/asurada/Kconfig.name A src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/board_info.txt A src/mainboard/google/asurada/boardid.c A src/mainboard/google/asurada/bootblock.c A src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/chromeos.fmd A src/mainboard/google/asurada/devicetree.cb A src/mainboard/google/asurada/mainboard.c A src/mainboard/google/asurada/memlayout.ld A src/mainboard/google/asurada/reset.c 12 files changed, 198 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/43963/10
CK HU has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 10:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43963/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43963/8//COMMIT_MSG@9 PS8, Line 9: firmware
Line exceeding 72 characters.
Done
https://review.coreboot.org/c/coreboot/+/43963/8/src/mainboard/google/asurad... File src/mainboard/google/asurada/Kconfig:
https://review.coreboot.org/c/coreboot/+/43963/8/src/mainboard/google/asurad... PS8, Line 1: ## : ## This file is part of the coreboot project. : ## : ## : ## This program is free software; you can redistribute it and/or modify : ## it under the terms of the GNU General Public License as published by : ## the Free Software Foundation; version 2 of the License. : ## : ## This program is distributed in the hope that it will be useful, : ## but WITHOUT ANY WARRANTY; without even the implied warranty of : ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : ## GNU General Public License for more details. : ##
Please use […]
Done
https://review.coreboot.org/c/coreboot/+/43963/8/src/mainboard/google/asurad... File src/mainboard/google/asurada/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43963/8/src/mainboard/google/asurad... PS8, Line 1: ## : ## This file is part of the coreboot project. : ## : ## : ## This program is free software; you can redistribute it and/or modify : ## it under the terms of the GNU General Public License as published by : ## the Free Software Foundation; version 2 of the License. : ## : ## This program is distributed in the hope that it will be useful, : ## but WITHOUT ANY WARRANTY; without even the implied warranty of : ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : ## GNU General Public License for more details. : ##
Please use […]
Done
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 10: Code-Review+1
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
Patch Set 10: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
mb/google/asurada: Add new MT8192 mainboard "Asurada"
The placeholder functions and build rules for generating a minimal firmware to run on MT8192 SOC based mainboard "Asurada".
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43963 Reviewed-by: Yu-Ping Wu yupingso@google.com Reviewed-by: Hung-Te Lin hungte@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/mainboard/google/asurada/Kconfig A src/mainboard/google/asurada/Kconfig.name A src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/board_info.txt A src/mainboard/google/asurada/boardid.c A src/mainboard/google/asurada/bootblock.c A src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/chromeos.fmd A src/mainboard/google/asurada/devicetree.cb A src/mainboard/google/asurada/mainboard.c A src/mainboard/google/asurada/memlayout.ld A src/mainboard/google/asurada/reset.c 12 files changed, 198 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig new file mode 100644 index 0000000..e1c96f0 --- /dev/null +++ b/src/mainboard/google/asurada/Kconfig @@ -0,0 +1,52 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Umbrella option to be selected by variant boards. +config BOARD_GOOGLE_ASURADA_COMMON + def_bool n + +if BOARD_GOOGLE_ASURADA_COMMON + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOOTBLOCK_CONSOLE + select SOC_MEDIATEK_MT8192 + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select SPI_FLASH + select SPI_FLASH_INCLUDE_ALL_DRIVERS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SPI + select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT + select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER + +config MAINBOARD_DIR + string + default "google/asurada" + +config MAINBOARD_PART_NUMBER + string + default "Asurada" if BOARD_GOOGLE_ASURADA + +config DRIVER_TPM_SPI_BUS + hex + default 0x0 + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 1 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x2 + +endif diff --git a/src/mainboard/google/asurada/Kconfig.name b/src/mainboard/google/asurada/Kconfig.name new file mode 100644 index 0000000..df3dc24 --- /dev/null +++ b/src/mainboard/google/asurada/Kconfig.name @@ -0,0 +1,5 @@ +comment "Asurada" + +config BOARD_GOOGLE_ASURADA + bool "-> Asurada" + select BOARD_GOOGLE_ASURADA_COMMON diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc new file mode 100644 index 0000000..3f5968a --- /dev/null +++ b/src/mainboard/google/asurada/Makefile.inc @@ -0,0 +1,14 @@ +bootblock-y += memlayout.ld +bootblock-y += bootblock.c + +verstage-y += memlayout.ld +verstage-y += reset.c + +romstage-y += memlayout.ld +romstage-y += boardid.c + +ramstage-y += memlayout.ld +ramstage-y += boardid.c +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c diff --git a/src/mainboard/google/asurada/board_info.txt b/src/mainboard/google/asurada/board_info.txt new file mode 100644 index 0000000..b8059ad --- /dev/null +++ b/src/mainboard/google/asurada/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Asurada MediaTek MT8192 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/asurada/boardid.c b/src/mainboard/google/asurada/boardid.c new file mode 100644 index 0000000..2c8efcd --- /dev/null +++ b/src/mainboard/google/asurada/boardid.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> + +/* board_id is provided by ec/google/chromeec/ec_boardid.c */ + +uint32_t sku_id(void) +{ + return 0; +} + +uint32_t ram_code(void) +{ + return 0; +} diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c new file mode 100644 index 0000000..5dcae8c --- /dev/null +++ b/src/mainboard/google/asurada/bootblock.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c new file mode 100644 index 0000000..8f9fa53 --- /dev/null +++ b/src/mainboard/google/asurada/chromeos.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <security/tpm/tis.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +} + +int get_write_protect_state(void) +{ + return 0; +} + +int tis_plat_irq_status(void) +{ + return 0; +} diff --git a/src/mainboard/google/asurada/chromeos.fmd b/src/mainboard/google/asurada/chromeos.fmd new file mode 100644 index 0000000..2635854 --- /dev/null +++ b/src/mainboard/google/asurada/chromeos.fmd @@ -0,0 +1,45 @@ +# Firmware Layout Description for Chrome OS. +# +# The size and address of every section must be aligned to at least 4K, except: +# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. +# +# 'FMAP' may be found by binary search so its starting address should be better +# aligned to larger values. +# +# For sections to be preserved on update, add (PRESERVE) to individual sections +# instead of a group section; otherwise the preserved data may be wrong if you +# resize or reorder sections inside a group. + +FLASH@0x0 8M { + WP_RO@0x0 4M { + RO_SECTION { + BOOTBLOCK 128K + FMAP 4K + COREBOOT(CBFS) + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 32K # At least 16K. + } + RW_SECTION_A 1500K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + RW_MISC 36K { + RW_VPD(PRESERVE) 16K # At least 8K. + RW_NVRAM(PRESERVE) 8K + RW_DDR_TRAINING(PRESERVE) 8K + RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + } + RW_SECTION_B 1500K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 0x100 + } + RW_SHARED 36K { # Will be force updated on recovery. + SHARED_DATA 4K # 4K or less for netboot params. + RW_UNUSED + } + RW_LEGACY(CBFS) 1M # Minimal 1M. +} diff --git a/src/mainboard/google/asurada/devicetree.cb b/src/mainboard/google/asurada/devicetree.cb new file mode 100644 index 0000000..0bdeec2 --- /dev/null +++ b/src/mainboard/google/asurada/devicetree.cb @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/mediatek/mt8192 + device cpu_cluster 0 on + device cpu 0 on end + end +end diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c new file mode 100644 index 0000000..e6040fa --- /dev/null +++ b/src/mainboard/google/asurada/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +static void mainboard_init(struct device *dev) +{ +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/asurada/memlayout.ld b/src/mainboard/google/asurada/memlayout.ld new file mode 100644 index 0000000..0f1fcec --- /dev/null +++ b/src/mainboard/google/asurada/memlayout.ld @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/asurada/reset.c b/src/mainboard/google/asurada/reset.c new file mode 100644 index 0000000..3a97ee5 --- /dev/null +++ b/src/mainboard/google/asurada/reset.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <reset.h> + +void do_board_reset(void) +{ +}
HAOUAS Elyes has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/43963 )
Change subject: mb/google/asurada: Add new MT8192 mainboard "Asurada" ......................................................................
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Angel Pons (Code Review) -
CK HU (Code Review)
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HAOUAS Elyes (Code Review)
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Hung-Te Lin (Code Review)
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Yu-Ping Wu (Code Review)