Change in coreboot[master]: soc/intel/alderlake: Update UART0 GPIO as per latest schematics
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47847 )
Change subject: soc/intel/alderlake: Update UART0 GPIO as per latest schematics ......................................................................
soc/intel/alderlake: Update UART0 GPIO as per latest schematics
UART0_RX: C8 -> H10 UART0_TX: C9 -> H11
GPIO PIN Mode: NF1 -> NF2
Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/uart.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/47847/1
diff --git a/src/soc/intel/alderlake/uart.c b/src/soc/intel/alderlake/uart.c index cdbf8ec..a3bdc4a 100644 --- a/src/soc/intel/alderlake/uart.c +++ b/src/soc/intel/alderlake/uart.c @@ -21,8 +21,8 @@ { .console_index = 0, .gpios = { - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0 RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0 TX */ }, }, {
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47847 )
Change subject: soc/intel/alderlake: Update UART0 GPIO as per latest schematics ......................................................................
Patch Set 1: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47847 )
Change subject: soc/intel/alderlake: Update UART0 GPIO as per latest schematics ......................................................................
soc/intel/alderlake: Update UART0 GPIO as per latest schematics
UART0_RX: C8 -> H10 UART0_TX: C9 -> H11
GPIO PIN Mode: NF1 -> NF2
Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47847 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/alderlake/uart.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/uart.c b/src/soc/intel/alderlake/uart.c index cdbf8ec..a3bdc4a 100644 --- a/src/soc/intel/alderlake/uart.c +++ b/src/soc/intel/alderlake/uart.c @@ -21,8 +21,8 @@ { .console_index = 0, .gpios = { - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0 RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0 TX */ }, }, {
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47847 )
Change subject: soc/intel/alderlake: Update UART0 GPIO as per latest schematics ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47847/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47847/2//COMMIT_MSG@7 PS2, Line 7: latest schematics Schematics for what? This is common SoC code, shouldn't this be dependent on the pinout for the SoC?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47847 )
Change subject: soc/intel/alderlake: Update UART0 GPIO as per latest schematics ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47847/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47847/2//COMMIT_MSG@7 PS2, Line 7: latest schematics
Schematics for what?
RVP schematics with ADL SoC
This is common SoC code, shouldn't this be dependent on the pinout for the SoC?
yes, we have previous schematics with ADL interposer hence such GPIO PIN out delta.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47847 )
Change subject: soc/intel/alderlake: Update UART0 GPIO as per latest schematics ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47847/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47847/2//COMMIT_MSG@7 PS2, Line 7: latest schematics
Schematics for what? […]
Oh okay. So, basically this matches the pinout for ADL now? That makes sense.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47847 )
Change subject: soc/intel/alderlake: Update UART0 GPIO as per latest schematics ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47847/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47847/2//COMMIT_MSG@7 PS2, Line 7: latest schematics
Oh okay. So, basically this matches the pinout for ADL now? That makes sense.
Yes Furquan, as we have lately migrate into ADL SOC so i expect few more GPIO changes come in enabling course.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47847 )
Change subject: soc/intel/alderlake: Update UART0 GPIO as per latest schematics ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47847/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47847/2//COMMIT_MSG@7 PS2, Line 7: latest schematics
Yes Furquan, as we have lately migrate into ADL SOC so i expect few more GPIO changes come in enabli […]
Ah, I didn't notice the "schematics" part. But schematics contain the SoC pinout, so I imagine it's also an option (even if the information is usually in the datasheet or EDS).
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47847 )
Change subject: soc/intel/alderlake: Update UART0 GPIO as per latest schematics ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47847/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47847/2//COMMIT_MSG@7 PS2, Line 7: latest schematics
Ah, I didn't notice the "schematics" part. […]
yes, Datasheet will also get updated with this details. 😊
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Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
-
Subrata Banik (Code Review)