Change in coreboot[master]: siemens/mc_apl3: Enable all PCIe root ports

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29505

Change subject: siemens/mc_apl3: Enable all PCIe root ports
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siemens/mc_apl3: Enable all PCIe root ports

Enable all PCIe root ports for this mainboard.

Change-Id: I62c7ba5048b4c2288bb502a78b9621edda333f2a
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
1 file changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/29505/1

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
index bb3bf6f..36d4dbb 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
@@ -59,12 +59,12 @@
    	device pci 0e.0 off end	# - Audio
    	device pci 11.0 on  end	# - ISH
    	device pci 12.0 on  end	# - SATA
-		device pci 13.0 on  end	# - RP 2 - PCIe A 0 - MACPHY
-		device pci 13.1 on  end	# - RP 3 - PCIe A 1 - MACPHY
-		device pci 13.2 off end	# - RP 4 - PCIe-A 2
-		device pci 13.3 off end	# - RP 5 - PCIe-A 3
-		device pci 14.0 on  end	# - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge
-		device pci 14.1 on  end	# - RP 1 - PCIe-B 1 - FPGA
+		device pci 13.0 on  end	# - RP 2 - PCIe A 0
+		device pci 13.1 on  end	# - RP 3 - PCIe A 1
+		device pci 13.2 on  end	# - RP 4 - PCIe-A 2
+		device pci 13.3 on  end	# - RP 5 - PCIe-A 3
+		device pci 14.0 on  end	# - RP 0 - PCIe-B 0
+		device pci 14.1 on  end	# - RP 1 - PCIe-B 1
    	device pci 15.0 on  end	# - XHCI
    	device pci 15.1 off end	# - XDCI
    	device pci 16.0 on	# - I2C 0