Change in coreboot[master]: soc/intel/baytrail: add LPEA resources to southcluster.asl

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48745 )

Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl
......................................................................

soc/intel/baytrail: add LPEA resources to southcluster.asl

The LPEA device memory resources, required by Windows drivers,
were not being set.  Allocate required resources per Intel's
Valleyview Tianocore reference code.

This patch alone is not sufficient for working audio under Windows
on Baytrail ChromeOS devices, but it is a necessary component.

Test: boot Windows on google/swanky, observe LPEA device working properly.

Change-Id: I7994d9b2c6e134c01b05cd7c61d309b6ba6e88e5
Signed-off-by: Matt DeVillier 
---
M src/soc/intel/baytrail/acpi/southcluster.asl
1 file changed, 28 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/48745/1

diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index e3997d7..f0fda15 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -136,11 +136,17 @@
    		0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
    		0x00010000,,, FSEG)

-	// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
+	// LPEA Memory Region (0x20000000-0x201FFFFF)
    DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
    		Cacheable, ReadWrite,
    		0x00000000, 0x00000000, 0x00000000, 0x00000000,
-			0x00000000,,, PMEM)
+			0x00000000,,, LMEM)
+
+	// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
+	DwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+			Cacheable, ReadWrite,
+			0x00000000, 0x00000000, 0x00000000, 0x00000000,
+                        0x00000000,,, PMEM)

// TPM Area (0xfed40000-0xfed44fff)
    DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
@@ -152,10 +158,27 @@
 Method (_CRS, 0, Serialized)
 {

+	/* Update LPEA resource area */
+	CreateDWordField (MCRS, ^LMEM._MIN, LMIN)
+	CreateDWordField (MCRS, ^LMEM._MAX, LMAX)
+	CreateDWordField (MCRS, ^LMEM._LEN, LLEN)
+	If (LAnd (LNotEqual (LPFW, Zero), LEqual (LPEN, One)))
+	{
+		Store (LPFW, LMIN)
+		Store (0x00100000, LLEN)
+		Subtract (Add (LMIN, LLEN), One, LMAX)
+	}
+	Else
+	{
+		Store (Zero, LMIN)
+		Store (Zero, LMAX)
+		Store (Zero, LLEN)
+	}
+
    /* Update PCI resource area */
-	CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
-	CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
-	CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+	CreateDWordField (MCRS, ^PMEM._MIN, PMIN)
+	CreateDWordField (MCRS, ^PMEM._MAX, PMAX)
+	CreateDWordField (MCRS, ^PMEM._LEN, PLEN)

/* TOLM is BMBOUND accessible from IOSF so is saved in NVS */
    Store (\TOLM, PMIN)

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48745 )

Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl
......................................................................

Patch Set 1: Code-Review+1

Pleas use the new ACPI Syntax.

[Matt DeVillier (Code Review)]

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48745 )

Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl
......................................................................

Patch Set 1:
> Patch Set 1: Code-Review+1
>
> Pleas use the new ACPI Syntax.

I was wanting to keep Baytrail/Braswell as consistent as possible before reformatting both. But can update this patch if preferred

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48745 )

Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl
......................................................................

Patch Set 1: Code-Review+1
> Patch Set 1:
> > Patch Set 1: Code-Review+1
> >
> > Pleas use the new ACPI Syntax.
>
> I was wanting to keep Baytrail/Braswell as consistent as possible before reformatting both. But can update this patch if preferred

I also prefer the newer ASL syntax. It would be nice to update Braswell to use the newer ASL syntax.

[Matt DeVillier (Code Review)]

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48745 )

Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl
......................................................................

Patch Set 1:
> Patch Set 1: Code-Review+1
>
> I also prefer the newer ASL syntax. It would be nice to update Braswell to use the newer ASL syntax.

does it really make sense to insert a block identical to the rest in the area with different syntax?

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48745 )

Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl
......................................................................

Patch Set 1: Code-Review+1

(2 comments)

https://review.coreboot.org/c/coreboot/+/48745/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/48745/1//COMMIT_MSG@10 
PS1, Line 10: Intel's
            : Valleyview Tianocore reference code
Could you please add a reference to the code, so it’s clear what commit is used?

https://review.coreboot.org/c/coreboot/+/48745/1//COMMIT_MSG@16 
PS1, Line 16: Windows
Please mention the version.

[Matt DeVillier (Code Review)]

Hello build bot (Jenkins), Paul Menzel, Angel Pons, Michael Niewöhner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48745

to look at the new patch set (#2).

Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl
......................................................................

soc/intel/baytrail: add LPEA resources to southcluster.asl

The LPEA device memory resources, required by Windows drivers,
were not being set.  Allocate required resources using
soc/intel/braswell/acpi/southcluster.asl as a reference

This patch alone is not sufficient for working audio under Windows
on Baytrail ChromeOS devices, but it is a necessary component.

Test: boot Windows 10 on google/swanky, observe LPEA device working properly.

Change-Id: I7994d9b2c6e134c01b05cd7c61d309b6ba6e88e5
Signed-off-by: Matt DeVillier 
---
M src/soc/intel/baytrail/acpi/southcluster.asl
1 file changed, 28 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/48745/2

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48745 )

Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/48745/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/48745/2//COMMIT_MSG@11 
PS2, Line 11: soc/intel/braswell/acpi/southcluster.asl as a reference
missing trailing period

[Matt DeVillier (Code Review)]

Hello build bot (Jenkins), Paul Menzel, Angel Pons, Michael Niewöhner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48745

to look at the new patch set (#3).

Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl
......................................................................

soc/intel/baytrail: add LPEA resources to southcluster.asl

The LPEA device memory resources, required by Windows drivers,
were not being set.  Allocate required resources using
soc/intel/braswell/acpi/southcluster.asl as a reference.

This patch alone is not sufficient for working audio under Windows
on Baytrail ChromeOS devices, but it is a necessary component.

Test: boot Windows 10 on google/swanky, observe LPEA device working properly.

Change-Id: I7994d9b2c6e134c01b05cd7c61d309b6ba6e88e5
Signed-off-by: Matt DeVillier 
---
M src/soc/intel/baytrail/acpi/southcluster.asl
1 file changed, 28 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/48745/3

[Matt DeVillier (Code Review)]

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48745 )

Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/48745/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/48745/2//COMMIT_MSG@11 
PS2, Line 11: soc/intel/braswell/acpi/southcluster.asl as a reference
> missing trailing period

Done

[Matt DeVillier (Code Review)]

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48745 )

Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/48745/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/48745/1//COMMIT_MSG@10 
PS1, Line 10: Intel's
            : Valleyview Tianocore reference code
> Could you please add a reference to the code, so it’s clear what commit is used?

Done

https://review.coreboot.org/c/coreboot/+/48745/1//COMMIT_MSG@16 
PS1, Line 16: Windows
> Please mention the version.

Done

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48745 )

Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl
......................................................................

Patch Set 3: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48745 )

Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl
......................................................................

soc/intel/baytrail: add LPEA resources to southcluster.asl

The LPEA device memory resources, required by Windows drivers,
were not being set.  Allocate required resources using
soc/intel/braswell/acpi/southcluster.asl as a reference.

This patch alone is not sufficient for working audio under Windows
on Baytrail ChromeOS devices, but it is a necessary component.

Test: boot Windows 10 on google/swanky, observe LPEA device working properly.

Change-Id: I7994d9b2c6e134c01b05cd7c61d309b6ba6e88e5
Signed-off-by: Matt DeVillier 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48745
Reviewed-by: Angel Pons 
Reviewed-by: Patrick Rudolph 
Reviewed-by: Paul Menzel 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/baytrail/acpi/southcluster.asl
1 file changed, 28 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Patrick Rudolph: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index f59f240..05d6b0d 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -136,11 +136,17 @@
    		0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
    		0x00010000,,, FSEG)

-	// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
+	// LPEA Memory Region (0x20000000-0x201FFFFF)
    DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
    		Cacheable, ReadWrite,
    		0x00000000, 0x00000000, 0x00000000, 0x00000000,
-			0x00000000,,, PMEM)
+			0x00000000,,, LMEM)
+
+	// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
+	DwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+			Cacheable, ReadWrite,
+			0x00000000, 0x00000000, 0x00000000, 0x00000000,
+                        0x00000000,,, PMEM)

// TPM Area (0xfed40000-0xfed44fff)
    DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
@@ -152,10 +158,27 @@
 Method (_CRS, 0, Serialized)
 {

+	/* Update LPEA resource area */
+	CreateDWordField (MCRS, ^LMEM._MIN, LMIN)
+	CreateDWordField (MCRS, ^LMEM._MAX, LMAX)
+	CreateDWordField (MCRS, ^LMEM._LEN, LLEN)
+	If (LAnd (LNotEqual (LPFW, Zero), LEqual (LPEN, One)))
+	{
+		Store (LPFW, LMIN)
+		Store (0x00100000, LLEN)
+		Subtract (Add (LMIN, LLEN), One, LMAX)
+	}
+	Else
+	{
+		Store (Zero, LMIN)
+		Store (Zero, LMAX)
+		Store (Zero, LLEN)
+	}
+
    /* Update PCI resource area */
-	CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
-	CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
-	CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+	CreateDWordField (MCRS, ^PMEM._MIN, PMIN)
+	CreateDWordField (MCRS, ^PMEM._MAX, PMAX)
+	CreateDWordField (MCRS, ^PMEM._LEN, PLEN)

/* TOLM is BMBOUND accessible from IOSF so is saved in NVS */
    Store (\TOLM, PMIN)