Change in coreboot[master]: mb/intel/tglrvp: Enable HECI interface

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42307 )

Change subject: mb/intel/tglrvp: Enable HECI interface
......................................................................

mb/intel/tglrvp: Enable HECI interface

This is to enable Intel ME communication interface HECI1 by
devicetree for PAVP with CSE Lite.
PAVP feature is enabled with CSE Lite SKU for Chrome and HECI1 interface
is required between kernel and CSE Lite.

BUG=None
TEST=Build and boot tglrvp. Run lspci and check pcie device
     00:16.0 Communication controller: Intel Corporation Device a0e0

Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705
Signed-off-by: Jamie Ryu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42307
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
2 files changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Jamie Ryu: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index d4390b0..a2d297d 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -12,6 +12,9 @@
    register "pmc_gpe0_dw1" = "GPP_D"
    register "pmc_gpe0_dw2" = "GPP_E"

+	# Enable heci1 communication
+	register "HeciEnabled" = "1"
+
    # FSP configuration
    register "SaGv" = "SaGv_Enabled"
    register "SmbusEnable" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 7a5cae1..c381d2e 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -12,6 +12,9 @@
    register "pmc_gpe0_dw1" = "GPP_D"
    register "pmc_gpe0_dw2" = "GPP_E"

+	# Enable heci1 communication
+	register "HeciEnabled" = "1"
+
    # FSP configuration
    register "SaGv" = "SaGv_Disabled"
    register "SmbusEnable" = "1"