Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46711 )
Change subject: cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN ......................................................................
cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN
Fix CID 1435825 and 1435826.
The CIDs discovered Integer handling issues: Potentially overflowing expression "1 << size_msb" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned).
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: If859521b44d9ec3ea744c751501b75d24e3b69e8 --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46711/1
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 284a113..cb7ecdc 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -484,9 +484,9 @@ * size. The maximum size is calculated by a function of the * min base bit set and maximum size bit set. */ if (addr_lsb > size_msb) - mtrr_size = 1 << size_msb; + mtrr_size = 1ULL << size_msb; else - mtrr_size = 1 << addr_lsb; + mtrr_size = 1ULL << addr_lsb;
if (var_state->prepare_msrs) prep_var_mtrr(var_state, base, mtrr_size, mtrr_type);
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46711 )
Change subject: cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/46711/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46711/1//COMMIT_MSG@9 PS1, Line 9: Fix CID 1435825 and 1435826. nit: Move next to the Signed-off-by line and write it as follows:
Fixes: CID 1435825 and 1435826
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46711 )
Change subject: cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN ......................................................................
Patch Set 1:
(1 comment)
Thanks!
https://review.coreboot.org/c/coreboot/+/46711/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46711/1//COMMIT_MSG@9 PS1, Line 9: Fix CID 1435825 and 1435826.
nit: Move next to the Signed-off-by line and write it as follows: […]
Done
Hello Marc Jones, build bot (Jenkins), Nico Huber, Angel Pons, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46711
to look at the new patch set (#2).
Change subject: cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN ......................................................................
cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN
Integer handling issues: Potentially overflowing expression "1 << size_msb" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned).
Fixes: CID 1435825 and 1435826
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: If859521b44d9ec3ea744c751501b75d24e3b69e8 --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46711/2
Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46711 )
Change subject: cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46711 )
Change subject: cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN ......................................................................
cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN
Integer handling issues: Potentially overflowing expression "1 << size_msb" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned).
Fixes: CID 1435825 and 1435826
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: If859521b44d9ec3ea744c751501b75d24e3b69e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46711 Reviewed-by: Marc Jones marc@marcjonesconsulting.com Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 284a113..cb7ecdc 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -484,9 +484,9 @@ * size. The maximum size is calculated by a function of the * min base bit set and maximum size bit set. */ if (addr_lsb > size_msb) - mtrr_size = 1 << size_msb; + mtrr_size = 1ULL << size_msb; else - mtrr_size = 1 << addr_lsb; + mtrr_size = 1ULL << addr_lsb;
if (var_state->prepare_msrs) prep_var_mtrr(var_state, base, mtrr_size, mtrr_type);
-
Angel Pons (Code Review) -
Jonathan Zhang (Code Review)
-
Marc Jones (Code Review)
-
Patrick Georgi (Code Review)