Change in coreboot[master]: mb/asrock/g41m-vs3-r2: Allow to set the fixed duty cycle from rtc nvram

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28714

Change subject: mb/asrock/g41m-vs3-r2: Allow to set the fixed duty cycle from rtc nvram
......................................................................

mb/asrock/g41m-vs3-r2: Allow to set the fixed duty cycle from rtc nvram

By default the SuperIO is strapped to set the fan duty cycle of the CPU fan to a
100%, which can be quite loud. This change makes it configurable.

This duty cycle will remain fixed afterwards but with w83627ehf linux module +
the fancontrol tool you can gain fine grained control. No proper fan control can
be implemented with the SuperIO's modes of operation as it seems that none of
the temps are correlated with the CPU temp (even in vendor BIOS). Newer ACPI
revisions might make this possible to implement this without the fancontrol
daemon.

This also fixes sensors 2 to thermistor mode (not the default diode mode).

Change-Id: Ifb5bbb578182e88f4f7ba4e0e47404241b1a1962
Signed-off-by: Arthur Heymans 
---
M src/mainboard/asrock/g41c-gs/Makefile.inc
M src/mainboard/asrock/g41c-gs/cmos.layout
A src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/Makefile.inc
A src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/mainboard.c
4 files changed, 95 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/28714/1

diff --git a/src/mainboard/asrock/g41c-gs/Makefile.inc b/src/mainboard/asrock/g41c-gs/Makefile.inc
index 82e72fb..cc9edb1 100644
--- a/src/mainboard/asrock/g41c-gs/Makefile.inc
+++ b/src/mainboard/asrock/g41c-gs/Makefile.inc
@@ -1,4 +1,6 @@
 ramstage-y += cstates.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c

+subdirs-y += variants/$(VARIANT_DIR)
+
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asrock/g41c-gs/cmos.layout b/src/mainboard/asrock/g41c-gs/cmos.layout
index 57c30ae..c64913a 100644
--- a/src/mainboard/asrock/g41c-gs/cmos.layout
+++ b/src/mainboard/asrock/g41c-gs/cmos.layout
@@ -61,9 +61,13 @@

# coreboot config options: northbridge
 432         4        e      11        gfx_uma_size
+
+# coreboot config options: superio
+436         2        e      10        fan_duty_cycle
 #435        549       r       0        unused

+
 # coreboot config options: check sums
 984         16       h       0        check_sum

@@ -91,6 +95,10 @@
 7     0     Disable
 7     1     Enable
 7     2     Keep
+10    0     100
+10    1     75
+10    2     50
+10    3     25
 11    6     64M
 11    7     128M
 11    8     256M
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/Makefile.inc b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/Makefile.inc
new file mode 100644
index 0000000..faf4971
--- /dev/null
+++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/Makefile.inc
@@ -0,0 +1 @@
+ramstage-y += mainboard.c
\ No newline at end of file
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/mainboard.c b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/mainboard.c
new file mode 100644
index 0000000..87bbc38
--- /dev/null
+++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/mainboard.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <device/device.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/io.h>
+
+/* Hardware Monitor */
+/* Must match devicetree */
+static u16 hwm_base = 0x290;
+
+static void hwm_write(u8 reg, u8 value)
+{
+	outb(reg, hwm_base + 0x05);
+	outb(value, hwm_base + 0x06);
+}
+
+static void hwm_bank(u8 bank)
+{
+	hwm_write(0x4e, bank);
+}
+
+enum duty_cycles {
+	DUTY_CYCLE_100 = 0,
+	DUTY_CYCLE_75 = 1,
+	DUTY_CYCLE_50 = 2,
+	DUTY_CYCLE_25 = 3,
+};
+
+static void hwm_setup(struct device *dev)
+{
+	enum duty_cycles duty_cycle = DUTY_CYCLE_75;
+	get_option(&duty_cycle, "fan_duty_cycle");
+	hwm_bank(0);
+	u8 reg;
+	switch (duty_cycle){
+	case DUTY_CYCLE_100:
+		reg = 0xff;
+		break;
+	default:
+	case DUTY_CYCLE_75:
+		reg = 0xff * 3 / 4;
+		break;
+	case DUTY_CYCLE_50:
+		reg = 0xff / 2;
+		break;
+	case DUTY_CYCLE_25:
+		reg = 0xff / 4;
+		break;
+	}
+	hwm_write(0x03, reg); /* CPU FAN PWM duty cycle*/
+	/* Default: both fans in manual mode, CPU fan PWM, Case fan DC */
+	hwm_write(0x04, 0x01);
+	hwm_bank(0x80);
+	hwm_write(0x5d, 0xa1); /* All Sensors Thermistor, not diode */
+	hwm_write(0x5e, 0x00);
+
+}
+
+/* mainboard_enable is executed as first thing after */
+/* enumerate_buses(). */
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->init = hwm_setup;
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("MAINBOARD")
+	.enable_dev = mainboard_enable,
+};