Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded

[Angel Pons (Code Review)]

Attention is currently required from: Arthur Heymans, Patrick Georgi, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Werner Zeh, Angel Pons, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 )

Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded
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Patch Set 2:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/62566/comment/80bf18d9_13b310d8 
PS2, Line 15: Now, in this scenario, the SPI
            : flash linear address range is not registered as a resource (since the
            : common SPI driver in src/soc/intel/common/block/spi is shared across
            : multiple SPI controllers and therefore cannot distinguish where the
            : flash is actually located at)
> Having boot firmware on eMMC wouldn't be such an issue even in uncached case I guess since eMMC prov […]

I wasn't thinking about the loading speed, I was considering the flash resource declaration. Only *SPI* flash would be attached to the fast SPI controller, the fast SPI controller could even be disabled on systems that boot off eMMC. That's why I don't want to declare the flash resource (i.e. memory-mapped SPI or eMMC) from the fast SPI controller device.