Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48189 )
Change subject: mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB ......................................................................
mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB
This change restricts SI_ME region to live below the 16MiB boundary to ensure that no regions cross the 16MiB boundary as the extended BIOS window checker for FMAP complains about it.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ib0838ff4c63b06b8dc169b40d3022965b2f2f8f9 --- M src/mainboard/intel/tglrvp/chromeos.fmd 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/48189/1
diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd index bfbd304..1e2e792 100644 --- a/src/mainboard/intel/tglrvp/chromeos.fmd +++ b/src/mainboard/intel/tglrvp/chromeos.fmd @@ -1,8 +1,8 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1081000 { + SI_ALL@0x0 0x1000000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x1000000 + SI_ME@0x81000 } SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 {
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48189 )
Change subject: mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB ......................................................................
Patch Set 1: Code-Review+1
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48189 )
Change subject: mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB ......................................................................
Patch Set 1: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48189 )
Change subject: mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB ......................................................................
mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB
This change restricts SI_ME region to live below the 16MiB boundary to ensure that no regions cross the 16MiB boundary as the extended BIOS window checker for FMAP complains about it.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ib0838ff4c63b06b8dc169b40d3022965b2f2f8f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48189 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Reviewed-by: Duncan Laurie dlaurie@chromium.org --- M src/mainboard/intel/tglrvp/chromeos.fmd 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd index bfbd304..1e2e792 100644 --- a/src/mainboard/intel/tglrvp/chromeos.fmd +++ b/src/mainboard/intel/tglrvp/chromeos.fmd @@ -1,8 +1,8 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1081000 { + SI_ALL@0x0 0x1000000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x1000000 + SI_ME@0x81000 } SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 {
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Duncan Laurie (Code Review) -
Furquan Shaikh (Code Review)
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Srinidhi N Kaushik (Code Review)