Change in coreboot[master]: broadwell: Align with haswell - coreboot-gerrit

20 Jun 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42620 )
Change subject: broadwell: Align with haswell
......................................................................
broadwell: Align with haswell
Tested with BUILD_TIMELESS=1, google/buddy does not change.
Change-Id: I2ca9eb464b911325acf32aec63b071c4d9ecf6c0
Signed-off-by: Angel Pons th3fanbus@gmail.com
---
M src/cpu/intel/broadwell/broadwell_init.c
M src/cpu/intel/broadwell/smmrelocate.c
M src/northbridge/intel/broadwell/acpi.c
M src/northbridge/intel/broadwell/bootblock.c
M src/northbridge/intel/broadwell/minihd.c
M src/northbridge/intel/broadwell/northbridge.c
M src/northbridge/intel/broadwell/report_platform.c
M src/southbridge/intel/wildcatpoint/bootblock.c
M src/southbridge/intel/wildcatpoint/ehci.c
M src/southbridge/intel/wildcatpoint/gpio.c
M src/southbridge/intel/wildcatpoint/hda.c
M src/southbridge/intel/wildcatpoint/iobp.c
M src/southbridge/intel/wildcatpoint/lpc.c
M src/southbridge/intel/wildcatpoint/me.c
M src/southbridge/intel/wildcatpoint/me_status.c
M src/southbridge/intel/wildcatpoint/pch.c
M src/southbridge/intel/wildcatpoint/pcie.c
M src/southbridge/intel/wildcatpoint/pmutil.c
M src/southbridge/intel/wildcatpoint/serialio.c
M src/southbridge/intel/wildcatpoint/smbus.c
M src/southbridge/intel/wildcatpoint/smi.c
M src/southbridge/intel/wildcatpoint/smihandler.c
M src/southbridge/intel/wildcatpoint/xhci.c
23 files changed, 457 insertions(+), 477 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/42620/1

diff --git a/src/cpu/intel/broadwell/broadwell_init.c b/src/cpu/intel/broadwell/broadwell_init.c
index 2ad6aea..5d26232 100644
--- a/src/cpu/intel/broadwell/broadwell_init.c
+++ b/src/cpu/intel/broadwell/broadwell_init.c
@@ -431,7 +431,7 @@
    /* Clear out pending MCEs */
    configure_mca();
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
    enable_lapic_tpr();
    setup_lapic();
diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c
index 2a307ef..5599c0b 100644
--- a/src/cpu/intel/broadwell/smmrelocate.c
+++ b/src/cpu/intel/broadwell/smmrelocate.c
@@ -12,10 +12,10 @@
 #include <cpu/intel/em64t101_save_state.h>
 #include <cpu/intel/smm_reloc.h>
 #include <console/console.h>
-#include <smp/node.h>
-#include <cpu/intel/broadwell/broadwell.h>
-#include <southbridge/intel/wildcatpoint/pci_devs.h>
 #include <northbridge/intel/broadwell/broadwell.h>
+#include <southbridge/intel/wildcatpoint/pci_devs.h>
+#include <smp/node.h>
+#include "broadwell.h"
static void update_save_state(int cpu, uintptr_t curr_smbase,
@@ -141,6 +141,7 @@
 {
    uintptr_t tseg_base;
    size_t tseg_size;
+
    u32 prmrr_base;
    u32 prmrr_size;
    int phys_bits;
@@ -254,11 +255,11 @@
void smm_lock(void)
 {
-	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
    /* LOCK the SMM memory window and enable normal SMM.
     * After running this function, only a full reset can
     * make the SMM registers writable again.
     */
    printk(BIOS_DEBUG, "Locking SMM.\n");
-	pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
+	pci_write_config8(pcidev_path_on_root(SA_DEVFN_ROOT), SMRAM,
+			D_LCK | G_SMRAME | C_BASE_SEG);
 }
diff --git a/src/northbridge/intel/broadwell/acpi.c b/src/northbridge/intel/broadwell/acpi.c
index df08537..1627074 100644
--- a/src/northbridge/intel/broadwell/acpi.c
+++ b/src/northbridge/intel/broadwell/acpi.c
@@ -25,8 +25,7 @@
    const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
-	if (igfx_dev && igfx_dev->enabled && gfxvtbar
-			&& gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
+	if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
    	unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
@@ -45,16 +44,16 @@
/* VTVC0BAR has to be set, enabled, and in 32-bit space */
    if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
+
    	const unsigned long tmp = current;
-		current += acpi_create_dmar_drhd(current,
-				DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
-		current += acpi_create_dmar_ds_ioapic(current,
-				2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
+		current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
+		current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS,
+						      PCH_IOAPIC_PCI_SLOT, 0);
+
    	size_t i;
    	for (i = 0; i < 8; ++i)
-			current += acpi_create_dmar_ds_msi_hpet(current,
-					0, PCH_HPET_PCI_BUS,
-					PCH_HPET_PCI_SLOT, i);
+			current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS,
+								PCH_HPET_PCI_SLOT, i);
    	acpi_dmar_drhd_fixup(tmp, current);
    }
diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c
index 89ff992..d661f57 100644
--- a/src/northbridge/intel/broadwell/bootblock.c
+++ b/src/northbridge/intel/broadwell/bootblock.c
@@ -10,16 +10,14 @@
    uint32_t reg;
/*
-	 * The "io" variant of the config access is explicitly used to
-	 * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
-	 * to true. That way all subsequent non-explicit config accesses use
-	 * MCFG. This code also assumes that bootblock_northbridge_init() is
-	 * the first thing called in the non-asm boot block code. The final
-	 * assumption is that no assembly code is using the
-	 * CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
+	 * The "io" variant of the config access is explicitly used to setup the PCIEXBAR
+	 * because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent
+	 * non-explicit config accesses use MCFG. This code also assumes that
+	 * bootblock_northbridge_init() is the first thing called in the non-asm
+	 * boot block code. The final assumption is that no assembly code is using
+	 * the CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
     *
-	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
-	 * 4GiB.
+	 * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
     */
    reg = 0;
    pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
diff --git a/src/northbridge/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c
index 7a93b9a..9df1047 100644
--- a/src/northbridge/intel/broadwell/minihd.c
+++ b/src/northbridge/intel/broadwell/minihd.c
@@ -12,30 +12,30 @@
static const u32 minihd_verb_table[] = {
    /* coreboot specific header */
-	0x80862808,	// Codec Vendor / Device ID: Intel Broadwell Mini-HD
-	0x80860101,	// Subsystem ID
-	0x00000004,	// Number of jacks
+	0x80862808,	/* Codec Vendor / Device ID: Intel Broadwell Mini-HD */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of jacks */
/* Enable 3rd Pin and Converter Widget */
    0x00878101,
/* Pin Widget 5 - PORT B */
-	0x00571C10,
-	0x00571D00,
-	0x00571E56,
-	0x00571F18,
+	0x00571c10,
+	0x00571d00,
+	0x00571e56,
+	0x00571f18,
/* Pin Widget 6 - PORT C */
-	0x00671C20,
-	0x00671D00,
-	0x00671E56,
-	0x00671F18,
+	0x00671c20,
+	0x00671d00,
+	0x00671e56,
+	0x00671f18,
/* Pin Widget 7 - PORT D */
-	0x00771C30,
-	0x00771D00,
-	0x00771E56,
-	0x00771F18,
+	0x00771c30,
+	0x00771d00,
+	0x00771e56,
+	0x00771f18,
/* Disable 3rd Pin and Converter Widget */
    0x00878100,
@@ -48,8 +48,8 @@
 static void minihd_init(struct device *dev)
 {
    struct resource *res;
-	u8 *base;
    u32 reg32;
+	u8 *base;
    int codec_mask, i;
/* Find base address */
@@ -80,8 +80,7 @@
    if (codec_mask) {
    	for (i = 3; i >= 0; i--) {
    		if (codec_mask & (1 << i))
-				hda_codec_init(base, i,
-					       sizeof(minihd_verb_table),
+				hda_codec_init(base, i, sizeof(minihd_verb_table),
    				       minihd_verb_table);
    	}
    }
@@ -92,10 +91,10 @@
 }
static struct device_operations minihd_ops = {
-	.read_resources		= &pci_dev_read_resources,
-	.set_resources		= &pci_dev_set_resources,
-	.enable_resources	= &pci_dev_enable_resources,
-	.init			= &minihd_init,
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= minihd_init,
    .ops_pci		= &broadwell_pci_ops,
 };
diff --git a/src/northbridge/intel/broadwell/northbridge.c b/src/northbridge/intel/broadwell/northbridge.c
index 5122fed..dab541a 100644
--- a/src/northbridge/intel/broadwell/northbridge.c
+++ b/src/northbridge/intel/broadwell/northbridge.c
@@ -16,8 +16,7 @@
 #include <southbridge/intel/wildcatpoint/ramstage.h>
 #include <northbridge/intel/broadwell/broadwell.h>
-static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
-			u32 *len)
+static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
 {
    u32 pciexbar_reg;
@@ -52,35 +51,31 @@
static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
 {
-	u32 bar;
+	u32 bar = pci_read_config32(dev, index);
-	bar = pci_read_config32(dev, index);
-
-	/* If not enabled don't report it. */
+	/* If not enabled don't report it */
    if (!(bar & 0x1))
    	return 0;
-	/* Knock down the enable bit. */
+	/* Knock down the enable bit */
    *base = bar & ~1;
return 1;
 }
-/* There are special BARs that actually are programmed in the MCHBAR. These
- * Intel special features, but they do consume resources that need to be
- * accounted for. */
-static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,
-			     u32 *len)
+/*
+ * There are special BARs that actually are programmed in the MCHBAR. These Intel special
+ * features, but they do consume resources that need to be accounted for.
+ */
+static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len)
 {
-	u32 bar;
+	u32 bar = MCHBAR32(index);
-	bar = MCHBAR32(index);
-
-	/* If not enabled don't report it. */
+	/* If not enabled don't report it */
    if (!(bar & 0x1))
    	return 0;
-	/* Knock down the enable bit. */
+	/* Knock down the enable bit */
    *base = bar & ~1;
return 1;
@@ -89,8 +84,7 @@
 struct fixed_mmio_descriptor {
    unsigned int index;
    u32 size;
-	int (*get_resource)(struct device *dev, unsigned int index,
-			    u32 *base, u32 *size);
+	int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size);
    const char *description;
 };
@@ -103,10 +97,7 @@
    { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
 };
-/*
- * Add all known fixed MMIO ranges that hang off the host bridge/memory
- * controller device.
- */
+/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */
 static void mc_add_fixed_mmio_resources(struct device *dev)
 {
    int i;
@@ -119,14 +110,13 @@
size = mc_fixed_resources[i].size;
    	index = mc_fixed_resources[i].index;
-		if (!mc_fixed_resources[i].get_resource(dev, index,
-							&base, &size))
+		if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size))
    		continue;
resource = new_resource(dev, mc_fixed_resources[i].index);
-		resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
-				  IORESOURCE_STORED | IORESOURCE_RESERVE |
-				  IORESOURCE_ASSIGNED;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+				  IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
+
    	resource->base = base;
    	resource->size = size;
    	printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
@@ -151,10 +141,10 @@
  * |     Usage DRAM           |
  * +--------------------------+ 0
  *
- * Some of the base registers above can be equal making the size of those
- * regions 0. The reason is because the memory controller internally subtracts
- * the base registers from each other to determine sizes of the regions. In
- * other words, the memory map is in a fixed order no matter what.
+ * Some of the base registers above can be equal, making the size of the regions within 0.
+ * This is because the memory controller internally subtracts the base registers from each
+ * other to determine sizes of the regions. In other words, the memory map regions are always
+ * in a fixed order, no matter what sizes they have.
  */
struct map_entry {
@@ -164,14 +154,13 @@
    const char *description;
 };
-static void read_map_entry(struct device *dev, struct map_entry *entry,
-			   uint64_t *result)
+static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result)
 {
    uint64_t value;
    uint64_t mask;
-	/* All registers are on a 1MiB granularity. */
-	mask = ((1ULL<<20)-1);
+	/* All registers have a 1MiB granularity */
+	mask = ((1ULL << 20) - 1);
    mask = ~mask;
value = 0;
@@ -198,12 +187,9 @@
    	.description = desc_,  \
    }
-#define MAP_ENTRY_BASE_64(reg_, desc_) \
-	MAP_ENTRY(reg_, 1, 0, desc_)
-#define MAP_ENTRY_LIMIT_64(reg_, desc_) \
-	MAP_ENTRY(reg_, 1, 1, desc_)
-#define MAP_ENTRY_BASE_32(reg_, desc_) \
-	MAP_ENTRY(reg_, 0, 0, desc_)
+#define MAP_ENTRY_BASE_32(reg_, desc_)	MAP_ENTRY(reg_, 0, 0, desc_)
+#define MAP_ENTRY_BASE_64(reg_, desc_)	MAP_ENTRY(reg_, 1, 0, desc_)
+#define MAP_ENTRY_LIMIT_64(reg_, desc_)	MAP_ENTRY(reg_, 1, 1, desc_)
enum {
    TOM_REG,
@@ -216,28 +202,29 @@
    BGSM_REG,
    BDSM_REG,
    TSEG_REG,
-	// Must be last.
-	NUM_MAP_ENTRIES
+	/* Must be last */
+	NUM_MAP_ENTRIES,
 };
static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
-	[TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
-	[TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
-	[MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
+	[TOM_REG]         = MAP_ENTRY_BASE_64(TOM, "TOM"),
+	[TOUUD_REG]       = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
+	[MESEG_BASE_REG]  = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
    [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"),
-	[REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
+	[REMAP_BASE_REG]  = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
    [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"),
-	[TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
-	[BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
-	[BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
-	[TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"),
+	[TOLUD_REG]       = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
+	[BDSM_REG]        = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
+	[BGSM_REG]        = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
+	[TSEG_REG]        = MAP_ENTRY_BASE_32(TSEG, "TESGMB"),	/* FIXME: typo */
 };
static void mc_read_map_entries(struct device *dev, uint64_t *values)
 {
    int i;
-	for (i = 0; i < NUM_MAP_ENTRIES; i++)
+	for (i = 0; i < NUM_MAP_ENTRIES; i++) {
    	read_map_entry(dev, &memory_map[i], &values[i]);
+	}
 }
static void mc_report_map_entries(struct device *dev, uint64_t *values)
@@ -247,22 +234,20 @@
    	printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
    	       memory_map[i].description, values[i]);
    }
-	/* One can validate the BDSM and BGSM against the GGC. */
+	/* One can validate the BDSM and BGSM against the GGC */
    printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
 }
static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
 {
-	unsigned long base_k, size_k;
-	unsigned long touud_k;
-	unsigned long index;
+	unsigned long base_k, size_k, touud_k, index;
    struct resource *resource;
    uint64_t mc_values[NUM_MAP_ENTRIES];
    unsigned long dpr_size = 0;
    u32 dpr_reg;
    struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
-	/* Read in the MAP registers and report their values. */
+	/* Read in the MAP registers and report their values */
    mc_read_map_entries(dev, &mc_values[0]);
    mc_report_map_entries(dev, &mc_values[0]);
@@ -280,33 +265,29 @@
/*
     * These are the host memory ranges that should be added:
-	 * - 0 -> 0xa0000: cacheable
-	 * - 0xc0000 -> TSEG : cacheable
-	 * - TESG -> BGSM: cacheable with standard MTRRs and reserved
-	 * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
-	 * - 4GiB -> TOUUD: cacheable
+	 * - 0 -> 0xa0000:    cacheable
+	 * - 0xc0000 -> TSEG: cacheable
+	 * - TSEG -> BGSM:    cacheable with standard MTRRs and reserved
+	 * - BGSM -> TOLUD:   not cacheable with standard MTRRs and reserved
+	 * - 4GiB -> TOUUD:   cacheable
     *
-	 * The default SMRAM space is reserved so that the range doesn't
-	 * have to be saved during S3 Resume. Once marked reserved the OS
-	 * cannot use the memory. This is a bit of an odd place to reserve
-	 * the region, but the CPU devices don't have dev_ops->read_resources()
-	 * called on them.
+	 * The default SMRAM space is reserved so that the range doesn't have to be saved
+	 * during S3 Resume. Once marked reserved the OS cannot use the memory. This is a
+	 * bit of an odd place to reserve the region, but the CPU devices don't have
+	 * dev_ops->read_resources() called on them.
     *
-	 * The range 0xa0000 -> 0xc0000 does not have any resources
-	 * associated with it to handle legacy VGA memory. If this range
-	 * is not omitted the mtrr code will setup the area as cacheable
-	 * causing VGA access to not work.
+	 * The range 0xa0000 -> 0xc0000 does not have any resources associated with it to
+	 * handle legacy VGA memory. If this range is not omitted the mtrr code will setup
+	 * the area as cacheable, causing VGA access to not work.
     *
-	 * The TSEG region is mapped as cacheable so that one can perform
-	 * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes
-	 * precedence over the existing MTRRs covering this region.
+	 * The TSEG region is mapped as cacheable so that one can perform SMRAM relocation
+	 * faster. Once the SMRR is enabled, the SMRR takes precedence over the existing
+	 * MTRRs covering this region.
     *
-	 * It should be noted that cacheable entry types need to be added in
-	 * order. The reason is that the current MTRR code assumes this and
-	 * falls over itself if it isn't.
+	 * It should be noted that cacheable entry types need to be added in order. The reason
+	 * is that the current MTRR code assumes this and falls over itself if it isn't.
     *
-	 * The resource index starts low and should not meet or exceed
-	 * PCI_BASE_ADDRESS_0.
+	 * The resource index starts low and should not meet or exceed PCI_BASE_ADDRESS_0.
     */
    index = *resource_cnt;
@@ -346,12 +327,11 @@
/* Reserve everything between A segment and 1MB:
     *
-	 * 0xa0000 - 0xbffff: legacy VGA
+	 * 0xa0000 - 0xbffff: Legacy VGA
     * 0xc0000 - 0xfffff: RAM
     */
    mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
-	reserved_ram_resource(dev, index++, (0xc0000 >> 10),
-				(0x100000 - 0xc0000) >> 10);
+	reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
if (CONFIG(CHROMEOS))
    	chromeos_reserve_ram_oops(dev, index++);
@@ -359,27 +339,24 @@
    *resource_cnt = index;
 }
-static void systemagent_read_resources(struct device *dev)
+static void mc_read_resources(struct device *dev)
 {
    int index = 0;
-	const bool vtd_capable =
-		!(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
+	const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
-	/* Read standard PCI resources. */
+	/* Read standard PCI resources */
    pci_dev_read_resources(dev);
-	/* Add all fixed MMIO resources. */
+	/* Add all fixed MMIO resources */
    mc_add_fixed_mmio_resources(dev);
-	/* Add VT-d MMIO resources if capable */
+	/* Add VT-d MMIO resources, if capable */
    if (vtd_capable) {
-		mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB,
-			GFXVT_BASE_SIZE / KiB);
-		mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB,
-			VTVC0_BASE_SIZE / KiB);
+		mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB);
+		mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB);
    }
-	/* Calculate and add DRAM resources. */
+	/* Calculate and add DRAM resources */
    mc_add_dram_resources(dev, &index);
 }
@@ -395,7 +372,7 @@
    MCHBAR8(MCH_PAIR) = pair;
/*
-	 * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
+	 * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU
     * that BIOS has initialized memory and power management
     */
    bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
@@ -410,7 +387,7 @@
 }
static struct device_operations systemagent_ops = {
-	.read_resources   = systemagent_read_resources,
+	.read_resources   = mc_read_resources,
    .acpi_fill_ssdt   = generate_cpu_entries,
    .set_resources    = pci_dev_set_resources,
    .enable_resources = pci_dev_enable_resources,
diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c
index 95d9c99..c963081 100644
--- a/src/northbridge/intel/broadwell/report_platform.c
+++ b/src/northbridge/intel/broadwell/report_platform.c
@@ -85,7 +85,7 @@
    	strcpy(cpu_string, "Platform info not available");
    } else {
    	u32 *p = (u32 *)cpu_string;
-		for (i = 2; i <= 4 ; i++) {
+		for (i = 2; i <= 4; i++) {
    		cpuidr = cpuid(index + i);
    		*p++ = cpuidr.eax;
    		*p++ = cpuidr.ebx;
diff --git a/src/southbridge/intel/wildcatpoint/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c
index 572ea09..55bb1c3 100644
--- a/src/southbridge/intel/wildcatpoint/bootblock.c
+++ b/src/southbridge/intel/wildcatpoint/bootblock.c
@@ -31,7 +31,7 @@
 static void enable_port80_on_lpc(void)
 {
    /* Enable port 80 POST on LPC. The chipset does this by default,
-	 * but it doesn't appear to hurt anything. */
+	   but it doesn't appear to hurt anything. */
    u32 gcs = RCBA32(GCS);
    gcs = gcs & ~0x4;
    RCBA32(GCS) = gcs;
diff --git a/src/southbridge/intel/wildcatpoint/ehci.c b/src/southbridge/intel/wildcatpoint/ehci.c
index 81ad62d..566b70f 100644
--- a/src/southbridge/intel/wildcatpoint/ehci.c
+++ b/src/southbridge/intel/wildcatpoint/ehci.c
@@ -8,8 +8,7 @@
 #include <southbridge/intel/wildcatpoint/ehci.h>
 #include <southbridge/intel/wildcatpoint/pch.h>
-static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
-	unsigned int device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
 {
    u8 access_cntl;
diff --git a/src/southbridge/intel/wildcatpoint/gpio.c b/src/southbridge/intel/wildcatpoint/gpio.c
index 62a7335..b0c0476 100644
--- a/src/southbridge/intel/wildcatpoint/gpio.c
+++ b/src/southbridge/intel/wildcatpoint/gpio.c
@@ -13,19 +13,19 @@
  * this GPIO maps to.  If this is not a PIRQ capable GPIO then
  * it will return -1.  The GPIO to PIRQ mapping is not linear.
  */
-static int gpio_to_pirq(int gpio)
+static int lp_gpio_to_pirq(int gpio)
 {
    switch (gpio) {
-	case 8:  return 0;	/* PIRQI */
-	case 9:  return 1;	/* PIRQJ */
-	case 10: return 2;	/* PIRQK */
-	case 13: return 3;	/* PIRQL */
-	case 14: return 4;	/* PIRQM */
-	case 45: return 5;	/* PIRQN */
-	case 46: return 6;	/* PIRQO */
-	case 47: return 7;	/* PIRQP */
-	case 48: return 8;	/* PIRQQ */
-	case 49: return 9;	/* PIRQR */
+	case  8: return  0;	/* PIRQI */
+	case  9: return  1;	/* PIRQJ */
+	case 10: return  2;	/* PIRQK */
+	case 13: return  3;	/* PIRQL */
+	case 14: return  4;	/* PIRQM */
+	case 45: return  5;	/* PIRQN */
+	case 46: return  6;	/* PIRQO */
+	case 47: return  7;	/* PIRQP */
+	case 48: return  8;	/* PIRQQ */
+	case 49: return  9;	/* PIRQR */
    case 50: return 10;	/* PIRQS */
    case 51: return 11;	/* PIRQT */
    case 52: return 12;	/* PIRQU */
@@ -36,9 +36,10 @@
    };
 }
-void init_gpios(const struct gpio_config config[])
+void init_gpios(const struct gpio_config map[])
 {
-	const struct gpio_config *entry;
+	const u16 gpio_base = GPIO_BASE_ADDRESS;
+	const struct gpio_config *config;
    u32 owner[3] = {0};
    u32 route[3] = {0};
    u32 irqen[3] = {0};
@@ -47,56 +48,58 @@
    u16 pirq2apic = 0;
    int set, bit, gpio = 0;
-	for (entry = config; entry->conf0 != GPIO_LIST_END; entry++, gpio++) {
+	for (config = map; config->conf0 != GPIO_LIST_END; config++, gpio++) {
    	if (gpio > MAX_GPIO_NUMBER)
    		break;
/* Setup Configuration registers 1 and 2 */
-		outl(entry->conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio));
-		outl(entry->conf1, GPIO_BASE_ADDRESS + GPIO_CONFIG1(gpio));
+		outl(config->conf0, gpio_base + GPIO_CONFIG0(gpio));
+		outl(config->conf1, gpio_base + GPIO_CONFIG1(gpio));
/* Determine set and bit based on GPIO number */
    	set = gpio >> 5;
    	bit = gpio % 32;
/* Apply settings to set specific bits */
-		owner[set] |= entry->owner << bit;
-		route[set] |= entry->route << bit;
-		irqen[set] |= entry->irqen << bit;
-		reset[set] |= entry->reset << bit;
+		owner[set] |= config->owner << bit;
+		route[set] |= config->route << bit;
+		irqen[set] |= config->irqen << bit;
+		reset[set] |= config->reset << bit;
if (set == 0)
-			blink |= entry->blink << bit;
+			blink |= config->blink << bit;
/* PIRQ to IO-APIC map */
-		if (entry->pirq == GPIO_PIRQ_APIC_ROUTE) {
-			set = gpio_to_pirq(gpio);
+		if (config->pirq == GPIO_PIRQ_APIC_ROUTE) {
+			set = lp_gpio_to_pirq(gpio);
    		if (set >= 0)
    			pirq2apic |= 1 << set;
    	}
    }
for (set = 0; set <= 2; set++) {
-		outl(owner[set], GPIO_BASE_ADDRESS + GPIO_OWNER(set));
-		outl(route[set], GPIO_BASE_ADDRESS + GPIO_ROUTE(set));
-		outl(irqen[set], GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set));
-		outl(reset[set], GPIO_BASE_ADDRESS + GPIO_RESET(set));
+		outl(owner[set], gpio_base + GPIO_OWNER(set));
+		outl(route[set], gpio_base + GPIO_ROUTE(set));
+		outl(irqen[set], gpio_base + GPIO_IRQ_IE(set));
+		outl(reset[set], gpio_base + GPIO_RESET(set));
    }
-	outl(blink, GPIO_BASE_ADDRESS + GPIO_BLINK);
-	outl(pirq2apic, GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN);
+	outl(blink, gpio_base + GPIO_BLINK);
+	outl(pirq2apic, gpio_base + GPIO_PIRQ_APIC_EN);
 }
int get_gpio(int gpio_num)
 {
+	const u16 gpio_base = GPIO_BASE_ADDRESS;
+
    if (gpio_num > MAX_GPIO_NUMBER)
    	return 0;
-	return !!(inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL);
+	return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL);
 }
/*
- * get a number comprised of multiple GPIO values. gpio_num_array points to
+ * Get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of gpio pin numbers to scan, terminated by -1.
  */
 unsigned int get_gpios(const int *gpio_num_array)
@@ -116,15 +119,16 @@
void set_gpio(int gpio_num, int value)
 {
+	const u16 gpio_base = GPIO_BASE_ADDRESS;
    u32 conf0;
if (gpio_num > MAX_GPIO_NUMBER)
    	return;
-	conf0 = inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num));
+	conf0 = inl(gpio_base + GPIO_CONFIG0(gpio_num));
    conf0 &= ~GPO_LEVEL_MASK;
    conf0 |= value << GPO_LEVEL_SHIFT;
-	outl(conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num));
+	outl(conf0, gpio_base + GPIO_CONFIG0(gpio_num));
 }
int gpio_is_native(int gpio_num)
diff --git a/src/southbridge/intel/wildcatpoint/hda.c b/src/southbridge/intel/wildcatpoint/hda.c
index 0dbe6cd..68e180d 100644
--- a/src/southbridge/intel/wildcatpoint/hda.c
+++ b/src/southbridge/intel/wildcatpoint/hda.c
@@ -2,16 +2,22 @@
#include <console/console.h>
 #include <device/device.h>
-#include <device/azalia_device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <device/mmio.h>
+#include <device/azalia_device.h>
 #include <soc/intel/common/hda_verb.h>
 #include <southbridge/intel/wildcatpoint/pch.h>
 #include <southbridge/intel/wildcatpoint/ramstage.h>
 #include <southbridge/intel/wildcatpoint/rcba.h>
+/* FIXME: For alignment with Haswell only */
+static inline bool pch_is_lp(void)
+{
+	return true;
+}
+
 static void codecs_init(u8 *base, u32 codec_mask)
 {
    int i;
@@ -19,27 +25,31 @@
    /* Can support up to 4 codecs */
    for (i = 3; i >= 0; i--) {
    	if (codec_mask & (1 << i))
-			hda_codec_init(base, i,
-				       cim_verb_data_size,
-				       cim_verb_data);
+			hda_codec_init(base, i, cim_verb_data_size, cim_verb_data);
    }
if (pc_beep_verbs_size)
    	hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
 }
-static void hda_pch_init(struct device *dev, u8 *base)
+static void azalia_pch_init(struct device *dev, u8 *base)
 {
    u8 reg8;
    u16 reg16;
    u32 reg32;
-	if (RCBA32(0x2030) & (1 << 31)) {
+	if (RCBA32(0x2030) & (1UL << 31)) {
    	reg32 = pci_read_config32(dev, 0x120);
    	reg32 &= 0xf8ffff01;
    	reg32 |= (1 << 25);
    	reg32 |= RCBA32(0x2030) & 0xfe;
    	pci_write_config32(dev, 0x120, reg32);
+
+		if (!pch_is_lp()) {
+			reg16 = pci_read_config16(dev, 0x78);
+			reg16 &= ~(1 << 11);
+			pci_write_config16(dev, 0x78, reg16);
+		}
    } else
    	printk(BIOS_DEBUG, "HDA: V1CTL disabled.\n");
@@ -48,37 +58,66 @@
    pci_write_config32(dev, 0x114, reg32);
// Set VCi enable bit
-	if (pci_read_config32(dev, 0x120) & ((1 << 24) |
-					     (1 << 25) | (1 << 26))) {
+	if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) {
    	reg32 = pci_read_config32(dev, 0x120);
-		reg32 &= ~(1 << 31);
+		if (pch_is_lp())
+			reg32 &= ~(1UL << 31);
+		else
+			reg32 |= (1UL << 31);
    	pci_write_config32(dev, 0x120, reg32);
    }
+	/* FIXME: Haswell does this, but we don't on Broadwell, c.f. hda_enable() */
+#if 0
+	reg8 = pci_read_config8(dev, 0x43);
+	if (pch_is_lp())
+		reg8 &= ~(1 << 6);
+	else
+		reg8 |= (1 << 4);
+	pci_write_config8(dev, 0x43, reg8);
+#endif
+
+	if (!pch_is_lp()) {
+		reg32 = pci_read_config32(dev, 0xc0);
+		reg32 |= (1 << 17);
+		pci_write_config32(dev, 0xc0, reg32);
+	}
+
    /* Additional programming steps */
    reg32 = pci_read_config32(dev, 0xc4);
-	reg32 |= (1 << 24);
+	if (pch_is_lp())
+		reg32 |= (1 << 24);
+	else
+		reg32 |= (1 << 14);
    pci_write_config32(dev, 0xc4, reg32);
+	if (!pch_is_lp()) {
+		reg32 = pci_read_config32(dev, 0xd0);
+		reg32 &= ~(1UL << 31);
+		pci_write_config32(dev, 0xd0, reg32);
+	}
+
    reg8 = pci_read_config8(dev, 0x40); // Audio Control
-	reg8 |= 1; // Select HDA mode
+	reg8 |= 1; // Select Azalia mode
    pci_write_config8(dev, 0x40, reg8);
reg8 = pci_read_config8(dev, 0x4d); // Docking Status
    reg8 &= ~(1 << 7); // Docking not supported
    pci_write_config8(dev, 0x4d, reg8);
-	reg16 = read32(base + 0x0012);
-	reg16 |= (1 << 0);
-	write32(base + 0x0012, reg16);
+	if (pch_is_lp()) {
+		reg16 = read32(base + 0x0012);
+		reg16 |= (1 << 0);
+		write32(base + 0x0012, reg16);
-	/* disable Auto Voltage Detector */
-	reg8 = pci_read_config8(dev, 0x42);
-	reg8 |= (1 << 2);
-	pci_write_config8(dev, 0x42, reg8);
+		/* disable Auto Voltage Detector */
+		reg8 = pci_read_config8(dev, 0x42);
+		reg8 |= (1 << 2);
+		pci_write_config8(dev, 0x42, reg8);
+	}
 }
-static void hda_init(struct device *dev)
+static void azalia_init(struct device *dev)
 {
    u8 *base;
    struct resource *res;
@@ -95,7 +134,7 @@
    /* Set Bus Master */
    pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
-	hda_pch_init(dev, base);
+	azalia_pch_init(dev, base);
codec_mask = hda_codec_detect(base);
@@ -134,11 +173,11 @@
 }
static struct device_operations hda_ops = {
-	.read_resources		= &pci_dev_read_resources,
-	.set_resources		= &pci_dev_set_resources,
-	.enable_resources	= &pci_dev_enable_resources,
-	.init			= &hda_init,
-	.enable			= &hda_enable,
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= azalia_init,
+	.enable			= hda_enable,
    .ops_pci		= &broadwell_pci_ops,
 };
diff --git a/src/southbridge/intel/wildcatpoint/iobp.c b/src/southbridge/intel/wildcatpoint/iobp.c
index 3332e26..72cb111 100644
--- a/src/southbridge/intel/wildcatpoint/iobp.c
+++ b/src/southbridge/intel/wildcatpoint/iobp.c
@@ -91,8 +91,12 @@
/* Check for successful transaction */
    status = RCBA16(IOBPS);
-	if (status & IOBPS_TX_MASK)
+	if (status & IOBPS_TX_MASK) {
    	printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address);
+		//return;
+	}
+
+	//printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data);
 }
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
diff --git a/src/southbridge/intel/wildcatpoint/lpc.c b/src/southbridge/intel/wildcatpoint/lpc.c
index 47d3e8f..11c962d 100644
--- a/src/southbridge/intel/wildcatpoint/lpc.c
+++ b/src/southbridge/intel/wildcatpoint/lpc.c
@@ -4,11 +4,11 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <option.h>
 #include <pc80/isa-dma.h>
 #include <pc80/i8259.h>
 #include <arch/io.h>
-#include <device/pci_ops.h>
 #include <arch/ioapic.h>
 #include <acpi/acpi.h>
 #include <cpu/x86/smm.h>
@@ -31,6 +31,17 @@
 #include <acpi/acpigen.h>
 #include <southbridge/intel/common/rtc.h>
+/* FIXME: For alignment with Haswell only */
+static inline bool pch_is_lp(void)
+{
+	return true;
+}
+
+/**
+ * Set miscellanous static southbridge features.
+ *
+ * @param dev PCI device with I/O APIC control registers
+ */
 static void pch_enable_ioapic(struct device *dev)
 {
    u32 reg32;
@@ -43,11 +54,11 @@
/* affirm full set of redirection table entries ("write once") */
    reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
-
-	/* PCH-LP has 39 redirection entries */
-	reg32 &= ~0x00ff0000;
-	reg32 |= 0x00270000;
-
+	if (pch_is_lp()) {
+		/* PCH-LP has 39 redirection entries */
+		reg32 &= ~0x00ff0000;
+		reg32 |= 0x00270000;
+	}
    io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/*
@@ -67,7 +78,8 @@
    		PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
 }
-/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
+/*
+ * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  * 0x00 - 0000 = Reserved
  * 0x01 - 0001 = Reserved
  * 0x02 - 0010 = Reserved
@@ -103,6 +115,11 @@
    pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
    pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+	/*
+	 * Eric Biederman once said we should let the OS do this.
+	 * I am not so sure anymore he was right.
+	 */
+
    for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
    	u8 int_pin = 0, int_line = 0;
@@ -112,18 +129,10 @@
    	int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) {
-		case 1: /* INTA# */
-			int_line = config->pirqa_routing;
-			break;
-		case 2: /* INTB# */
-			int_line = config->pirqb_routing;
-			break;
-		case 3: /* INTC# */
-			int_line = config->pirqc_routing;
-			break;
-		case 4: /* INTD# */
-			int_line = config->pirqd_routing;
-			break;
+		case 1: /* INTA# */ int_line = config->pirqa_routing; break;
+		case 2: /* INTB# */ int_line = config->pirqb_routing; break;
+		case 3: /* INTC# */ int_line = config->pirqc_routing; break;
+		case 4: /* INTD# */ int_line = config->pirqd_routing; break;
    	}
if (!int_line)
@@ -141,7 +150,8 @@
    config_t *config = config_of(dev);
    int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
-	/* Which state do we want to goto after g3 (power restored)?
+	/*
+	 * Which state do we want to go to after G3 (power restored)?
     * 0 == S0 Full On
     * 1 == S5 Soft Off
     *
@@ -411,9 +421,8 @@
static void pch_set_acpi_mode(void)
 {
-	if (!acpi_is_wakeup_s3()) {
+	if (!acpi_is_wakeup_s3())
    	apm_control(APM_CNT_ACPI_DISABLE);
-	}
 }
static void lpc_init(struct device *dev)
@@ -500,8 +509,7 @@
  * Note: this function assumes there is no overlap with the default LPC device's
  * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
  */
-static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size,
-				    int index)
+static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index)
 {
    struct resource *res;
@@ -514,12 +522,11 @@
    res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
-static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value,
-					 int index)
+static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index)
 {
    /*
     * Check if the register is enabled. If so and the base exceeds the
-	 * device's default claim range add the resource.
+	 * device's default, claim range and add the resource.
     */
    if (reg_value & 1) {
    	u16 base = reg_value & 0xfffc;
@@ -540,8 +547,7 @@
    res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* GPIOBASE */
-	pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS,
-				GPIO_BASE_SIZE, GPIO_BASE);
+	pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GPIO_BASE);
/* PMBASE */
    pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE);
@@ -572,7 +578,7 @@
    	memset(gnvs, 0, sizeof(global_nvs_t));
 }
-static void southcluster_inject_dsdt(const struct device *device)
+static void southbridge_inject_dsdt(const struct device *device)
 {
    global_nvs_t *gnvs;
@@ -641,13 +647,23 @@
    fadt->gpe0_blk = pmbase + GPE0_STS(0);
    fadt->gpe1_blk = 0;
-	fadt->pm1_evt_len = 4;
+	/*
+	 * Some of the lengths here are doubled. This is because they describe
+	 * blocks containing two registers, where the size of each register
+	 * is found by halving the block length. See Table 5-34 and section
+	 * 4.8.3 of the ACPI specification for details.
+	 */
+	fadt->pm1_evt_len = 2 * 2;
    fadt->pm1_cnt_len = 2;
    fadt->pm2_cnt_len = 1;
    fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 32;
+	if (pch_is_lp())
+		fadt->gpe0_blk_len = 2 * 16;
+	else
+		fadt->gpe0_blk_len = 2 * 8;
    fadt->gpe1_blk_len = 0;
    fadt->gpe1_base = 0;
+
    fadt->p_lvl2_lat = 1;
    fadt->p_lvl3_lat = 87;
    fadt->flush_size = 1024;
@@ -659,55 +675,60 @@
    fadt->century = 0x00;
    fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
-	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
-			ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
-			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+	fadt->flags = ACPI_FADT_WBINVD |
+		      ACPI_FADT_C1_SUPPORTED |
+		      ACPI_FADT_C2_MP_SUPPORTED |
+		      ACPI_FADT_SLEEP_BUTTON |
+		      ACPI_FADT_RESET_REGISTER |
+		      ACPI_FADT_SEALED_CASE |
+		      ACPI_FADT_S4_RTC_WAKE |
+		      ACPI_FADT_PLATFORM_CLOCK;
-	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
    fadt->reset_reg.bit_width = 8;
    fadt->reset_reg.bit_offset = 0;
    fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
    fadt->reset_reg.addrl = 0xcf9;
    fadt->reset_reg.addrh = 0;
+
    fadt->reset_value = 6;
-	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
    fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
    fadt->x_pm1a_evt_blk.bit_offset = 0;
    fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
    fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
    fadt->x_pm1a_evt_blk.addrh = 0x0;
-	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
    fadt->x_pm1b_evt_blk.bit_width = 0;
    fadt->x_pm1b_evt_blk.bit_offset = 0;
    fadt->x_pm1b_evt_blk.access_size = 0;
    fadt->x_pm1b_evt_blk.addrl = 0x0;
    fadt->x_pm1b_evt_blk.addrh = 0x0;
-	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
    fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
    fadt->x_pm1a_cnt_blk.bit_offset = 0;
    fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
    fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
    fadt->x_pm1a_cnt_blk.addrh = 0x0;
-	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
    fadt->x_pm1b_cnt_blk.bit_width = 0;
    fadt->x_pm1b_cnt_blk.bit_offset = 0;
    fadt->x_pm1b_cnt_blk.access_size = 0;
    fadt->x_pm1b_cnt_blk.addrl = 0x0;
    fadt->x_pm1b_cnt_blk.addrh = 0x0;
-	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
    fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
    fadt->x_pm2_cnt_blk.bit_offset = 0;
    fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
    fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
    fadt->x_pm2_cnt_blk.addrh = 0x0;
-	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
    fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
    fadt->x_pm_tmr_blk.bit_offset = 0;
    fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
@@ -725,10 +746,9 @@
    fadt->x_gpe0_blk.bit_offset = 0;
    fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
    fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
-	fadt->x_gpe0_blk.addrh = 0;
+	fadt->x_gpe0_blk.addrh = 0x0;
-
-	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
    fadt->x_gpe1_blk.bit_width = 0;
    fadt->x_gpe1_blk.bit_offset = 0;
    fadt->x_gpe1_blk.access_size = 0;
@@ -736,9 +756,9 @@
    fadt->x_gpe1_blk.addrh = 0x0;
 }
-static unsigned long broadwell_write_acpi_tables(const struct device *device,
-						 unsigned long current,
-						 struct acpi_rsdp *rsdp)
+static unsigned long southbridge_write_acpi_tables(const struct device *device,
+						   unsigned long current,
+						   struct acpi_rsdp *rsdp)
 {
    if (CONFIG(INTEL_PCH_UART_CONSOLE))
    	current = acpi_write_dbg2_pci_uart(rsdp, current,
@@ -749,13 +769,13 @@
 }
static struct device_operations device_ops = {
-	.read_resources		= &pch_lpc_read_resources,
-	.set_resources		= &pci_dev_set_resources,
-	.enable_resources	= &pci_dev_enable_resources,
-	.acpi_inject_dsdt	= southcluster_inject_dsdt,
-	.write_acpi_tables      = broadwell_write_acpi_tables,
-	.init			= &lpc_init,
-	.scan_bus		= &scan_static_bus,
+	.read_resources		= pch_lpc_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.acpi_inject_dsdt	= southbridge_inject_dsdt,
+	.write_acpi_tables	= southbridge_write_acpi_tables,
+	.init			= lpc_init,
+	.scan_bus		= scan_static_bus,
    .ops_pci		= &broadwell_pci_ops,
 };
diff --git a/src/southbridge/intel/wildcatpoint/me.c b/src/southbridge/intel/wildcatpoint/me.c
index 3b1998e..9520d13 100644
--- a/src/southbridge/intel/wildcatpoint/me.c
+++ b/src/southbridge/intel/wildcatpoint/me.c
@@ -82,7 +82,6 @@
 /*
  * ME/MEI access helpers using memcpy to avoid aliasing.
  */
-
 static inline void mei_read_dword_ptr(void *ptr, int offset)
 {
    u32 dword = read32(mei_base_address + offset);
@@ -264,8 +263,8 @@
    return 0;
 }
-static int mei_send_header(u8 me_address, u8 host_address,
-			   void *header, int header_len, int complete)
+static int mei_send_header(u8 me_address, u8 host_address, void *header, int header_len,
+			   int complete)
 {
    struct mei_header mei = {
    	.client_address = me_address,
@@ -276,8 +275,7 @@
    return mei_send_packet(&mei, header);
 }
-static int mei_recv_msg(void *header, int header_bytes,
-			void *rsp_data, int rsp_bytes)
+static int mei_recv_msg(void *header, int header_bytes, void *rsp_data, int rsp_bytes)
 {
    struct mei_header mei_rsp;
    struct mei_csr me, host;
@@ -336,8 +334,8 @@
/* Make sure caller passed a buffer with enough space */
    if (ndata != (rsp_bytes >> 2)) {
-		printk(BIOS_ERR, "ME: not enough room in response buffer: "
-		       "%u != %u\n", ndata, rsp_bytes >> 2);
+		printk(BIOS_ERR, "ME: not enough room in response buffer: %u != %u\n",
+		       ndata, rsp_bytes >> 2);
    	return -1;
    }
@@ -376,8 +374,7 @@
    	return 0;
/* Read header and data */
-	if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp),
-			 rsp_data, rsp_bytes) < 0)
+	if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp), rsp_data, rsp_bytes) < 0)
    	return -1;
if (!mkhi_rsp.is_response ||
@@ -434,7 +431,7 @@
 }
/*
- * mbp clear routine. This will wait for the ME to indicate that
+ * MBP clear routine. This will wait for the ME to indicate that
  * the MBP has been read and cleared.
  */
 static void intel_me_mbp_clear(struct device *dev)
@@ -487,8 +484,7 @@
    };
/* Send request and wait for response */
-	if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32),
-			      &cap_msg, sizeof(cap_msg)) < 0) {
+	if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), &cap_msg, sizeof(cap_msg)) < 0) {
    	printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
    	return -1;
    }
@@ -507,20 +503,20 @@
    		return;
    }
-	print_cap("Full Network manageability", cap->full_net);
-	print_cap("Regular Network manageability", cap->std_net);
-	print_cap("Manageability", cap->manageability);
-	print_cap("IntelR Anti-Theft (AT)", cap->intel_at);
-	print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
-	print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
-	print_cap("ICC Over Clocking", cap->icc_over_clocking);
-	print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
-	print_cap("IPV6", cap->ipv6);
-	print_cap("KVM Remote Control (KVM)", cap->kvm);
-	print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
-	print_cap("Virtual LAN (VLAN)", cap->vlan);
-	print_cap("TLS", cap->tls);
-	print_cap("Wireless LAN (WLAN)", cap->wlan);
+	print_cap("Full Network manageability",			cap->full_net);
+	print_cap("Regular Network manageability",		cap->std_net);
+	print_cap("Manageability",				cap->manageability);
+	print_cap("IntelR Anti-Theft (AT)",			cap->intel_at);
+	print_cap("IntelR Capability Licensing Service (CLS)",	cap->intel_cls);
+	print_cap("IntelR Power Sharing Technology (MPC)",	cap->intel_mpc);
+	print_cap("ICC Over Clocking",				cap->icc_over_clocking);
+	print_cap("Protected Audio Video Path (PAVP)",		cap->pavp);
+	print_cap("IPV6",					cap->ipv6);
+	print_cap("KVM Remote Control (KVM)",			cap->kvm);
+	print_cap("Outbreak Containment Heuristic (OCH)",	cap->och);
+	print_cap("Virtual LAN (VLAN)",				cap->vlan);
+	print_cap("TLS",					cap->tls);
+	print_cap("Wireless LAN (WLAN)",			cap->wlan);
 }
/* Send END OF POST message to the ME */
@@ -602,13 +598,12 @@
    u16 reg16;
/* S3 path will have hidden this device already */
-	if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0)
+	if (!mei_base_address || mei_base_address == (u8 *)0xfffffff0)
    	return;
/* Make sure IO is disabled */
    reg16 = pci_read_config16(dev, PCI_COMMAND);
-	reg16 &= ~(PCI_COMMAND_MASTER |
-		   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+	reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
    pci_write_config16(dev, PCI_COMMAND, reg16);
/* Hide the PCI device */
@@ -634,6 +629,7 @@
    	printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n");
    	return -1;
    }
+
    printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
    return 0;
 }
diff --git a/src/southbridge/intel/wildcatpoint/me_status.c b/src/southbridge/intel/wildcatpoint/me_status.c
index d11b26c..fc65fc9 100644
--- a/src/southbridge/intel/wildcatpoint/me_status.c
+++ b/src/southbridge/intel/wildcatpoint/me_status.c
@@ -47,7 +47,7 @@
    [ME_HFS_STATE_M3]	= "M3 without UMA",
    [ME_HFS_STATE_M0]	= "M0 without UMA",
    [ME_HFS_STATE_BRINGUP]	= "Bring up",
-	[ME_HFS_STATE_ERROR]	= "M0 without UMA but with error"
+	[ME_HFS_STATE_ERROR]	= "M0 without UMA but with error",
 };
/* HFS[19:16] Current Operation Mode Values */
@@ -56,7 +56,7 @@
    [ME_HFS_MODE_DEBUG]	= "Debug",
    [ME_HFS_MODE_DIS]	= "Soft Temporary Disable",
    [ME_HFS_MODE_OVER_JMPR]	= "Security Override via Jumper",
-	[ME_HFS_MODE_OVER_MEI]	= "Security Override via MEI Message"
+	[ME_HFS_MODE_OVER_MEI]	= "Security Override via MEI Message",
 };
/* HFS[15:12] Error Code Values */
@@ -64,7 +64,7 @@
    [ME_HFS_ERROR_NONE]	= "No Error",
    [ME_HFS_ERROR_UNCAT]	= "Uncategorized Failure",
    [ME_HFS_ERROR_IMAGE]	= "Image Failure",
-	[ME_HFS_ERROR_DEBUG]	= "Debug Failure"
+	[ME_HFS_ERROR_DEBUG]	= "Debug Failure",
 };
/* HFS2[31:28] ME Progress Code */
@@ -75,121 +75,78 @@
    [ME_HFS2_PHASE_POLICY]		= "Policy Module",
    [ME_HFS2_PHASE_MODULE_LOAD]	= "Module Loading",
    [ME_HFS2_PHASE_UNKNOWN]		= "Unknown",
-	[ME_HFS2_PHASE_HOST_COMM]	= "Host Communication"
+	[ME_HFS2_PHASE_HOST_COMM]	= "Host Communication",
 };
/* HFS2[27:24] Power Management Event */
 static const char *me_pmevent_values[] = {
-	[ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] =
-	"Clean Moff->Mx wake",
-	[ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] =
-	"Moff->Mx wake after an error",
-	[ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] =
-	"Clean global reset",
-	[ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] =
-	"Global reset after an error",
-	[ME_HFS2_PMEVENT_CLEAN_ME_RESET] =
-	"Clean Intel ME reset",
-	[ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] =
-	"Intel ME reset due to exception",
-	[ME_HFS2_PMEVENT_PSEUDO_ME_RESET] =
-	"Pseudo-global reset",
-	[ME_HFS2_PMEVENT_S0MO_SXM3] =
-	"S0/M0->Sx/M3",
-	[ME_HFS2_PMEVENT_SXM3_S0M0] =
-	"Sx/M3->S0/M0",
-	[ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] =
-	"Non-power cycle reset",
-	[ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] =
-	"Power cycle reset through M3",
-	[ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] =
-	"Power cycle reset through Moff",
-	[ME_HFS2_PMEVENT_SXMX_SXMOFF] =
-	"Sx/Mx->Sx/Moff"
+	[ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE]		= "Clean Moff->Mx wake",
+	[ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR]		= "Moff->Mx wake after an error",
+	[ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET]		= "Clean global reset",
+	[ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR]	= "Global reset after an error",
+	[ME_HFS2_PMEVENT_CLEAN_ME_RESET]		= "Clean Intel ME reset",
+	[ME_HFS2_PMEVENT_ME_RESET_EXCEPTION]		= "Intel ME reset due to exception",
+	[ME_HFS2_PMEVENT_PSEUDO_ME_RESET]		= "Pseudo-global reset",
+	[ME_HFS2_PMEVENT_S0MO_SXM3]			= "S0/M0->Sx/M3",
+	[ME_HFS2_PMEVENT_SXM3_S0M0]			= "Sx/M3->S0/M0",
+	[ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET]		= "Non-power cycle reset",
+	[ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3]		= "Power cycle reset through M3",
+	[ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF]		= "Power cycle reset through Moff",
+	[ME_HFS2_PMEVENT_SXMX_SXMOFF]			= "Sx/Mx->Sx/Moff",
 };
/* Progress Code 0 states */
 static const char *me_progress_rom_values[] = {
-	[ME_HFS2_STATE_ROM_BEGIN] = "BEGIN",
-	[ME_HFS2_STATE_ROM_DISABLE] = "DISABLE"
+	[ME_HFS2_STATE_ROM_BEGIN]	= "BEGIN",
+	[ME_HFS2_STATE_ROM_DISABLE]	= "DISABLE",
 };
/* Progress Code 1 states */
 static const char *me_progress_bup_values[] = {
-	[ME_HFS2_STATE_BUP_INIT] =
-	"Initialization starts",
-	[ME_HFS2_STATE_BUP_DIS_HOST_WAKE] =
-	"Disable the host wake event",
-	[ME_HFS2_STATE_BUP_FLOW_DET] =
-	"Flow determination start process",
-	[ME_HFS2_STATE_BUP_VSCC_ERR] =
-	"Error reading/matching the VSCC table in the descriptor",
-	[ME_HFS2_STATE_BUP_CHECK_STRAP] =
-	"Check to see if straps say ME DISABLED",
-	[ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] =
-	"Timeout waiting for PWROK",
-	[ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] =
-	"Possibly handle BUP manufacturing override strap",
-	[ME_HFS2_STATE_BUP_M3] =
-	"Bringup in M3",
-	[ME_HFS2_STATE_BUP_M0] =
-	"Bringup in M0",
-	[ME_HFS2_STATE_BUP_FLOW_DET_ERR] =
-	"Flow detection error",
-	[ME_HFS2_STATE_BUP_M3_CLK_ERR] =
-	"M3 clock switching error",
-	[ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] =
-	"Host error - CPU reset timeout, DID timeout, memory missing",
-	[ME_HFS2_STATE_BUP_M3_KERN_LOAD] =
-	"M3 kernel load",
-	[ME_HFS2_STATE_BUP_T32_MISSING] =
-	"T34 missing - cannot program ICC",
-	[ME_HFS2_STATE_BUP_WAIT_DID] =
-	"Waiting for DID BIOS message",
-	[ME_HFS2_STATE_BUP_WAIT_DID_FAIL] =
-	"Waiting for DID BIOS message failure",
-	[ME_HFS2_STATE_BUP_DID_NO_FAIL] =
-	"DID reported no error",
-	[ME_HFS2_STATE_BUP_ENABLE_UMA] =
-	"Enabling UMA",
-	[ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] =
-	"Enabling UMA error",
-	[ME_HFS2_STATE_BUP_SEND_DID_ACK] =
-	"Sending DID Ack to BIOS",
-	[ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] =
-	"Sending DID Ack to BIOS error",
-	[ME_HFS2_STATE_BUP_M0_CLK] =
-	"Switching clocks in M0",
-	[ME_HFS2_STATE_BUP_M0_CLK_ERR] =
-	"Switching clocks in M0 error",
-	[ME_HFS2_STATE_BUP_TEMP_DIS] =
-	"ME in temp disable",
-	[ME_HFS2_STATE_BUP_M0_KERN_LOAD] =
-	"M0 kernel load",
+	[ME_HFS2_STATE_BUP_INIT]		= "Initialization starts",
+	[ME_HFS2_STATE_BUP_DIS_HOST_WAKE]	= "Disable the host wake event",
+	[ME_HFS2_STATE_BUP_FLOW_DET]		= "Flow determination start process",
+	[ME_HFS2_STATE_BUP_VSCC_ERR]		= "Error reading/matching the VSCC table in the descriptor",
+	[ME_HFS2_STATE_BUP_CHECK_STRAP]		= "Check to see if straps say ME DISABLED",
+	[ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT]	= "Timeout waiting for PWROK",
+	[ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP]	= "Possibly handle BUP manufacturing override strap",
+	[ME_HFS2_STATE_BUP_M3]			= "Bringup in M3",
+	[ME_HFS2_STATE_BUP_M0]			= "Bringup in M0",
+	[ME_HFS2_STATE_BUP_FLOW_DET_ERR]	= "Flow detection error",
+	[ME_HFS2_STATE_BUP_M3_CLK_ERR]		= "M3 clock switching error",
+	[ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = "Host error - CPU reset timeout, DID timeout, memory missing",
+	[ME_HFS2_STATE_BUP_M3_KERN_LOAD]	= "M3 kernel load",
+	[ME_HFS2_STATE_BUP_T32_MISSING]		= "T34 missing - cannot program ICC",
+	[ME_HFS2_STATE_BUP_WAIT_DID]		= "Waiting for DID BIOS message",
+	[ME_HFS2_STATE_BUP_WAIT_DID_FAIL]	= "Waiting for DID BIOS message failure",
+	[ME_HFS2_STATE_BUP_DID_NO_FAIL]		= "DID reported no error",
+	[ME_HFS2_STATE_BUP_ENABLE_UMA]		= "Enabling UMA",
+	[ME_HFS2_STATE_BUP_ENABLE_UMA_ERR]	= "Enabling UMA error",
+	[ME_HFS2_STATE_BUP_SEND_DID_ACK]	= "Sending DID Ack to BIOS",
+	[ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR]	= "Sending DID Ack to BIOS error",
+	[ME_HFS2_STATE_BUP_M0_CLK]		= "Switching clocks in M0",
+	[ME_HFS2_STATE_BUP_M0_CLK_ERR]		= "Switching clocks in M0 error",
+	[ME_HFS2_STATE_BUP_TEMP_DIS]		= "ME in temp disable",
+	[ME_HFS2_STATE_BUP_M0_KERN_LOAD]	= "M0 kernel load",
 };
/* Progress Code 3 states */
 static const char *me_progress_policy_values[] = {
-	[ME_HFS2_STATE_POLICY_ENTRY] = "Entry into Policy Module",
-	[ME_HFS2_STATE_POLICY_RCVD_S3] = "Received S3 entry",
-	[ME_HFS2_STATE_POLICY_RCVD_S4] = "Received S4 entry",
-	[ME_HFS2_STATE_POLICY_RCVD_S5] = "Received S5 entry",
-	[ME_HFS2_STATE_POLICY_RCVD_UPD] = "Received UPD entry",
-	[ME_HFS2_STATE_POLICY_RCVD_PCR] = "Received PCR entry",
-	[ME_HFS2_STATE_POLICY_RCVD_NPCR] = "Received NPCR entry",
-	[ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE] = "Received host wake",
-	[ME_HFS2_STATE_POLICY_RCVD_AC_DC] = "Received AC<>DC switch",
-	[ME_HFS2_STATE_POLICY_RCVD_DID] = "Received DRAM Init Done",
-	[ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND] =
-	"VSCC Data not found for flash device",
-	[ME_HFS2_STATE_POLICY_VSCC_INVALID] =
-	"VSCC Table is not valid",
-	[ME_HFS2_STATE_POLICY_FPB_ERR] =
-	"Flash Partition Boundary is outside address space",
-	[ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] =
-	"ME cannot access the chipset descriptor region",
-	[ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] =
-	"Required VSCC values for flash parts do not match",
+	[ME_HFS2_STATE_POLICY_ENTRY]		= "Entry into Policy Module",
+	[ME_HFS2_STATE_POLICY_RCVD_S3]		= "Received S3 entry",
+	[ME_HFS2_STATE_POLICY_RCVD_S4]		= "Received S4 entry",
+	[ME_HFS2_STATE_POLICY_RCVD_S5]		= "Received S5 entry",
+	[ME_HFS2_STATE_POLICY_RCVD_UPD]		= "Received UPD entry",
+	[ME_HFS2_STATE_POLICY_RCVD_PCR]		= "Received PCR entry",
+	[ME_HFS2_STATE_POLICY_RCVD_NPCR]	= "Received NPCR entry",
+	[ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE]	= "Received host wake",
+	[ME_HFS2_STATE_POLICY_RCVD_AC_DC]	= "Received AC<>DC switch",
+	[ME_HFS2_STATE_POLICY_RCVD_DID]		= "Received DRAM Init Done",
+	[ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND]	= "VSCC Data not found for flash device",
+	[ME_HFS2_STATE_POLICY_VSCC_INVALID]	= "VSCC Table is not valid",
+	[ME_HFS2_STATE_POLICY_FPB_ERR]		= "Flash Partition Boundary is outside address space",
+	[ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR]	= "ME cannot access the chipset descriptor region",
+	[ME_HFS2_STATE_POLICY_VSCC_NO_MATCH]	= "Required VSCC values for flash parts do not match",
 };
void intel_me_status(void)
diff --git a/src/southbridge/intel/wildcatpoint/pch.c b/src/southbridge/intel/wildcatpoint/pch.c
index 1ac2967..efee415 100644
--- a/src/southbridge/intel/wildcatpoint/pch.c
+++ b/src/southbridge/intel/wildcatpoint/pch.c
@@ -185,8 +185,7 @@
/* Ensure memory, io, and bus master are all disabled */
    	reg16 = pci_read_config16(dev, PCI_COMMAND);
-		reg16 &= ~(PCI_COMMAND_MASTER |
-			   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+		reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
    	pci_write_config16(dev, PCI_COMMAND, reg16);
/* Disable this device if possible */
diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c
index 4515ffb..4f9a34a 100644
--- a/src/southbridge/intel/wildcatpoint/pcie.c
+++ b/src/southbridge/intel/wildcatpoint/pcie.c
@@ -18,7 +18,7 @@
 #include <delay.h>
/* Low Power variant has 6 root ports. */
-#define NUM_ROOT_PORTS 6
+#define MAX_NUM_ROOT_PORTS 6
struct root_port_config {
    /* RPFN is a write-once register so keep a copy until it is written */
@@ -34,7 +34,7 @@
    int coalesce;
    int gbe_port;
    int num_ports;
-	struct device *ports[NUM_ROOT_PORTS];
+	struct device *ports[MAX_NUM_ROOT_PORTS];
 };
static struct root_port_config rpc;
@@ -110,7 +110,7 @@
    if (root_port_is_first(dev)) {
    	rpc.orig_rpfn = RCBA32(RPFN);
    	rpc.new_rpfn = rpc.orig_rpfn;
-		rpc.num_ports = NUM_ROOT_PORTS;
+		rpc.num_ports = MAX_NUM_ROOT_PORTS;
    	rpc.gbe_port = -1;
    	/* RP0 f5[3:0] = 0101b*/
    	pci_update_config8(dev, 0xf5, ~0xa, 0x5);
@@ -338,8 +338,7 @@
    	}
    }
-	printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n",
-	       rpc.orig_rpfn, rpc.new_rpfn);
+	printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", rpc.orig_rpfn, rpc.new_rpfn);
    RCBA32(RPFN) = rpc.new_rpfn;
 }
@@ -372,8 +371,7 @@
    /* Check Root Port Configuration. */
    switch (rp) {
    case 2:
-		/* Root Port 2 is disabled for all lane configurations
-		 * but config 00b (4x1 links). */
+		/* Root Port 2 is disabled for all lane configs except 00b (4x1 links). */
    	if ((rpc.strpfusecfg1 >> 14) & 0x3) {
    		root_port_mark_disable(dev);
    		return;
@@ -387,8 +385,7 @@
    	}
    	break;
    case 4:
-		/* Root Port 4 is disabled in configs 11b (1x4 links)
-		 * and 10b (2x2 links). */
+		/* Root Port 4 is disabled in configs 11b (1x4 links) and 10b (2x2 links). */
    	if ((rpc.strpfusecfg1 >> 14) & 0x2) {
    		root_port_mark_disable(dev);
    		return;
@@ -473,8 +470,7 @@
if (do_aspm) {
    	/* Set ASPM bits in MPC2 register. */
-		pci_update_config32(dev, 0xd4, ~(0x3 << 2),
-			(1 << 4) | (0x2 << 2));
+		pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2));
/* Set unique clock exit latency in MPC register. */
    	pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
@@ -583,6 +579,7 @@
    pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Set Cache Line Size to 0x10 */
+	// This has no effect but the OS might expect it
    pci_write_config8(dev, 0x0c, 0x10);
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
diff --git a/src/southbridge/intel/wildcatpoint/pmutil.c b/src/southbridge/intel/wildcatpoint/pmutil.c
index b66fb87..3024efd 100644
--- a/src/southbridge/intel/wildcatpoint/pmutil.c
+++ b/src/southbridge/intel/wildcatpoint/pmutil.c
@@ -90,10 +90,10 @@
 static u16 print_pm1_status(u16 pm1_sts)
 {
    const char *pm1_sts_bits[] = {
-		[0] = "TMROF",
-		[4] = "BM",
-		[5] = "GBL",
-		[8] = "PWRBTN",
+		[0]  = "TMROF",
+		[4]  = "BM",
+		[5]  = "GBL",
+		[8]  = "PWRBTN",
    	[10] = "RTC",
    	[11] = "PRBTNOR",
    	[14] = "PCIEXPWAK",
@@ -122,7 +122,6 @@
    outw(events, ACPI_BASE_ADDRESS + PM1_EN);
 }
-
 /*
  * SMI
  */
@@ -130,7 +129,7 @@
 /* Clear and return SMI status register */
 static u32 reset_smi_status(void)
 {
-	u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS);
+	const u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS);
    outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS);
    return smi_sts;
 }
@@ -139,13 +138,13 @@
 static u32 print_smi_status(u32 smi_sts)
 {
    const char *smi_sts_bits[] = {
-		[2] = "BIOS",
-		[3] = "LEGACY_USB",
-		[4] = "SLP_SMI",
-		[5] = "APM",
-		[6] = "SWSMI_TMR",
-		[8] = "PM1",
-		[9] = "GPE0",
+		[2]  = "BIOS",
+		[3]  = "LEGACY_USB",
+		[4]  = "SLP_SMI",
+		[5]  = "APM",
+		[6]  = "SWSMI_TMR",
+		[8]  = "PM1",
+		[9]  = "GPE0",
    	[10] = "GPI",
    	[11] = "MCSMI",
    	[12] = "DEVMON",
@@ -193,7 +192,6 @@
    outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
 }
-
 /*
  * ALT_GP_SMI
  */
@@ -270,13 +268,13 @@
 static u32 print_tco_status(u32 tco_sts)
 {
    const char *tco_sts_bits[] = {
-		[0] = "NMI2SMI",
-		[1] = "SW_TCO",
-		[2] = "TCO_INT",
-		[3] = "TIMEOUT",
-		[7] = "NEWCENTURY",
-		[8] = "BIOSWR",
-		[9] = "DMISCI",
+		[0]  = "NMI2SMI",
+		[1]  = "SW_TCO",
+		[2]  = "TCO_INT",
+		[3]  = "TIMEOUT",
+		[7]  = "NEWCENTURY",
+		[8]  = "BIOSWR",
+		[9]  = "DMISCI",
    	[10] = "DMISMI",
    	[12] = "DMISERR",
    	[13] = "SLVSEL",
@@ -318,7 +316,7 @@
  */
/* Clear a GPE0 status and return events that are enabled and active */
-static u32 reset_gpe(u16 sts_reg, u16 en_reg)
+static u32 reset_gpe_status(u16 sts_reg, u16 en_reg)
 {
    u32 gpe0_sts = inl(ACPI_BASE_ADDRESS + sts_reg);
    u32 gpe0_en = inl(ACPI_BASE_ADDRESS + en_reg);
@@ -359,11 +357,11 @@
 u32 clear_gpe_status(void)
 {
    const char *gpe0_sts_3_bits[] = {
-		[1] = "HOTPLUG",
-		[2] = "SWGPE",
-		[6] = "TCO_SCI",
-		[7] = "SMB_WAK",
-		[9] = "PCI_EXP",
+		[1]  = "HOTPLUG",
+		[2]  = "SWGPE",
+		[6]  = "TCO_SCI",
+		[7]  = "SMB_WAK",
+		[9]  = "PCI_EXP",
    	[10] = "BATLOW",
    	[11] = "PME",
    	[12] = "ME",
@@ -372,10 +370,10 @@
    	[18] = "WADT"
    };
-	print_gpe_gpio(reset_gpe(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0);
-	print_gpe_gpio(reset_gpe(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32);
-	print_gpe_gpio(reset_gpe(GPE0_STS(GPE_94_64), GPE0_EN(GPE_94_64)), 64);
-	return print_gpe_status(reset_gpe(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)),
+	print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0);
+	print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32);
+	print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_94_64), GPE0_EN(GPE_94_64)), 64);
+	return print_gpe_status(reset_gpe_status(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)),
    			gpe0_sts_3_bits);
 }
diff --git a/src/southbridge/intel/wildcatpoint/serialio.c b/src/southbridge/intel/wildcatpoint/serialio.c
index 3dbbc6e..613f2ac 100644
--- a/src/southbridge/intel/wildcatpoint/serialio.c
+++ b/src/southbridge/intel/wildcatpoint/serialio.c
@@ -271,10 +271,10 @@
 }
static struct device_operations device_ops = {
-	.read_resources		= &pci_dev_read_resources,
-	.set_resources		= &serialio_set_resources,
-	.enable_resources	= &pci_dev_enable_resources,
-	.init			= &serialio_init,
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= serialio_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= serialio_init,
    .ops_pci		= &broadwell_pci_ops,
 };
diff --git a/src/southbridge/intel/wildcatpoint/smbus.c b/src/southbridge/intel/wildcatpoint/smbus.c
index b8177e5..5cfd277 100644
--- a/src/southbridge/intel/wildcatpoint/smbus.c
+++ b/src/southbridge/intel/wildcatpoint/smbus.c
@@ -1,16 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/io.h>
 #include <device/device.h>
 #include <device/path.h>
 #include <device/smbus.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <device/smbus_host.h>
 #include <southbridge/intel/wildcatpoint/iomap.h>
 #include <southbridge/intel/wildcatpoint/ramstage.h>
 #include <southbridge/intel/wildcatpoint/smbus.h>
-#include <device/smbus_host.h>
static void pch_smbus_init(struct device *dev)
 {
@@ -54,8 +53,8 @@
 }
static struct smbus_bus_operations lops_smbus_bus = {
-	.read_byte	= lsmbus_read_byte,
-	.write_byte	= lsmbus_write_byte,
+	.read_byte  = lsmbus_read_byte,
+	.write_byte = lsmbus_write_byte,
 };
static void smbus_read_resources(struct device *dev)
diff --git a/src/southbridge/intel/wildcatpoint/smi.c b/src/southbridge/intel/wildcatpoint/smi.c
index 75eeb02d..c6f8361 100644
--- a/src/southbridge/intel/wildcatpoint/smi.c
+++ b/src/southbridge/intel/wildcatpoint/smi.c
@@ -39,7 +39,8 @@
    enable_pm1(pm1_events);
    disable_gpe(PME_B0_EN);
-	/* Enable SMI generation:
+	/*
+	 * Enable SMI generation:
     *  - on APMC writes (io 0xb2)
     *  - on writes to SLP_EN (sleep states)
     *  - on writes to GBL_RLS (bios commands)
diff --git a/src/southbridge/intel/wildcatpoint/smihandler.c b/src/southbridge/intel/wildcatpoint/smihandler.c
index 98e26ca..782ba14 100644
--- a/src/southbridge/intel/wildcatpoint/smihandler.c
+++ b/src/southbridge/intel/wildcatpoint/smihandler.c
@@ -69,12 +69,12 @@
    for (slot = 0; slot < 0x20; slot++) {
    	for (func = 0; func < 8; func++) {
    		u16 reg16;
-
    		pci_devfn_t dev = PCI_DEV(bus, slot, func);
+
    		val = pci_read_config32(dev, PCI_VENDOR_ID);
if (val == 0xffffffff || val == 0x00000000 ||
-				val == 0x0000ffff || val == 0xffff0000)
+			    val == 0x0000ffff || val == 0xffff0000)
    			continue;
/* Disable Bus Mastering for this one device */
@@ -86,7 +86,7 @@
    		hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
    		hdr &= 0x7f;
    		if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-				hdr == PCI_HEADER_TYPE_CARDBUS) {
+			    hdr == PCI_HEADER_TYPE_CARDBUS) {
    			unsigned int buses;
    			buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
    			busmaster_disable_on_bus((buses >> 8) & 0xff);
@@ -96,10 +96,9 @@
 }
/*
- * Turn off the backlight if it is on, and wait for the specified
- * backlight off delay.  This will allow panel power timings to meet
- * spec and prevent brief garbage on the screen when turned off
- * during firmware with power button triggered SMI.
+ * Turn off the backlight if it is on, and wait for the specified backlight off delay.
+ * This will allow panel power timings to meet spec and prevent brief garbage on the
+ * screen when turned off during firmware with power button triggered SMI.
  */
 static void backlight_off(void)
 {
@@ -255,11 +254,11 @@
    for (node = 0; node < CONFIG_MAX_CPUS; node++) {
    	state = smm_get_save_state(node);
-		/* Check for Synchronous IO (bit0==1) */
+		/* Check for Synchronous IO (bit0 == 1) */
    	if (!(state->io_misc_info & (1 << 0)))
    		continue;
-		/* Make sure it was a write (bit4==0) */
+		/* Make sure it was a write (bit4 == 0) */
    	if (state->io_misc_info & (1 << 4))
    		continue;
@@ -372,11 +371,9 @@
 {
    u16 pm1_sts = clear_pm1_status();
-	/* While OSPM is not active, poweroff immediately
-	 * on a power button event.
-	 */
+	/* While OSPM is not active, poweroff immediately on a power button event */
    if (pm1_sts & PWRBTN_STS) {
-		/* power button pressed */
+		/* Power button pressed */
    	elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON);
    	disable_pm1_control(-1UL);
    	enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));
@@ -431,8 +428,7 @@
    		 * box.
    		 */
    		printk(BIOS_DEBUG, "Switching back to RO\n");
-			pci_write_config32(PCH_DEV_LPC, BIOS_CNTL,
-					   (bios_cntl & ~1));
+			pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, bios_cntl & ~1);
    	} /* No else for now? */
    } else if (tco_sts & (1 << 3)) { /* TIMEOUT */
    	/* Handle TCO timeout */
@@ -454,6 +450,7 @@
 static void southbridge_smi_monitor(void)
 {
 #define IOTRAP(x) (trap_sts & (1 << x))
+
    u32 trap_sts, trap_cycle;
    u32 data, mask = 0;
    int i;
@@ -475,13 +472,12 @@
    	return;
    }
-	/* IOTRAP(2) currently unused
-	 * IOTRAP(1) currently unused */
+	/* IOTRAP(2) currently unused */
+	/* IOTRAP(1) currently unused */
/* IOTRAP(0) SMIC */
    if (IOTRAP(0)) {
-		// It's a write
-		if (!(trap_cycle & (1 << 24))) {
+		if (!(trap_cycle & (1 << 24))) { // It's a write
    		printk(BIOS_DEBUG, "SMI1 command\n");
    		data = RCBA32(0x1e18);
    		data &= mask;
@@ -492,15 +488,15 @@
    	// Fall through to debug
    }
-	printk(BIOS_DEBUG, "  trapped io address = 0x%x\n",
-	       trap_cycle & 0xfffc);
-	for (i = 0; i < 4; i++)
+	printk(BIOS_DEBUG, "  trapped io address = 0x%x\n", trap_cycle & 0xfffc);
+
+	for (i = 0; i < 4; i++) {
    	if (IOTRAP(i))
    		printk(BIOS_DEBUG, "  TRAP = %d\n", i);
+	}
    printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
    printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
-	printk(BIOS_DEBUG, "  read/write: %s\n",
-	       (trap_cycle & (1 << 24)) ? "read" : "write");
+	printk(BIOS_DEBUG, "  read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
if (!(trap_cycle & (1 << 24))) {
    	/* Write Cycle */
@@ -549,16 +545,14 @@
/**
  * @brief Interrupt handler for SMI#
- *
- * @param smm_revision revision of the smm state save map
  */
-
 void southbridge_smi_handler(void)
 {
    int i;
    u32 smi_sts;
-	/* We need to clear the SMI status registers, or we won't see what's
+	/*
+	 * We need to clear the SMI status registers, or we won't see what's
     * happening in the following calls.
     */
    smi_sts = clear_smi_status();
@@ -570,8 +564,7 @@
    			southbridge_smi[i]();
    		} else {
    			printk(BIOS_DEBUG,
-				       "SMI_STS[%d] occurred, but no "
-				       "handler available.\n", i);
+				       "SMI_STS[%d] occurred, but no handler available.\n", i);
    		}
    	}
    }
diff --git a/src/southbridge/intel/wildcatpoint/xhci.c b/src/southbridge/intel/wildcatpoint/xhci.c
index cef2bed..2469cfd 100644
--- a/src/southbridge/intel/wildcatpoint/xhci.c
+++ b/src/southbridge/intel/wildcatpoint/xhci.c
@@ -185,7 +185,7 @@
 }
 #else /* !__SIMPLE_DEVICE__ */
-static void xhci_init(struct device *dev)
+static void usb_xhci_init(struct device *dev)
 {
    struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
    u16 reg16;
@@ -207,8 +207,8 @@
    .read_resources		= pci_dev_read_resources,
    .set_resources		= pci_dev_set_resources,
    .enable_resources	= pci_dev_enable_resources,
+	.init			= usb_xhci_init,
    .ops_pci		= &broadwell_pci_ops,
-	.init			= xhci_init,
 };
static const unsigned short pci_device_ids[] = {
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/42620
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2ca9eb464b911325acf32aec63b071c4d9ecf6c0
Gerrit-Change-Number: 42620
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons th3fanbus@gmail.com
Gerrit-MessageType: newchange



    