Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47079 )
Change subject: sc7280: HACK PATCH: To support SPI-NOR driver for Rumi ......................................................................
sc7280: HACK PATCH: To support SPI-NOR driver for Rumi
- In Rumi, GPIO emulation is not present and CS assert/deassert is done through controller - In soc, CS assert/deassert is done using GPIO - Disable SBL_EN bit in QSPI master config register
Change-Id: I2a53c1094b90ac7896e835864848467c52d2a03e Signed-off-by: Roja Rani Yarubandi rojay@codeaurora.org --- M src/soc/qualcomm/sc7280/qspi.c 1 file changed, 10 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/47079/1
diff --git a/src/soc/qualcomm/sc7280/qspi.c b/src/soc/qualcomm/sc7280/qspi.c index 3c627a5..fba8f89 100644 --- a/src/soc/qualcomm/sc7280/qspi.c +++ b/src/soc/qualcomm/sc7280/qspi.c @@ -123,15 +123,17 @@ * So to support read transfers that are not preceded by write, set * transfer fragment bit = 1 */ - next->fragment = 1; + next->fragment = 0; next->reserved2 = 0; next->length = 0; next->bounce_src = 0; next->bounce_dst = 0; next->bounce_length = 0;
- if (current) + if (current) { current->next_descriptor = (uint32_t)(uintptr_t) next; + current->fragment = 1; + }
return next; } @@ -169,6 +171,7 @@ ptr = (void *)(uintptr_t) desc->data_address;
if (write) { + desc->fragment = 1; memcpy(ptr, data, data_bytes); } else { desc->bounce_src = (uint32_t)(uintptr_t) ptr; @@ -190,10 +193,12 @@ desc->data_address = (uint32_t)(uintptr_t) data; desc->length = data_bytes;
- if (write) + if (write) { + desc->fragment = 1; dcache_clean_by_mva(data, data_bytes); - else + } else { dcache_invalidate_by_mva(data, data_bytes); + } }
static void queue_data(uint8_t *data, uint32_t data_bytes, @@ -235,7 +240,7 @@ tx_data_delay = 0;
mstr_config = (tx_data_oe_delay << TX_DATA_OE_DELAY_SHIFT) | - (tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) | + (tx_data_delay << TX_DATA_DELAY_SHIFT) | (spi_mode << SPI_MODE_SHIFT) | (PIN_HOLDN) | (FB_CLK_EN) |
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47079
to look at the new patch set (#2).
Change subject: HACK sc7280: To support SPI-NOR driver for Rumi ......................................................................
HACK sc7280: To support SPI-NOR driver for Rumi
- In Rumi, GPIO emulation is not present and CS assert/deassert is done through controller - In soc, CS assert/deassert is done using GPIO - Disable SBL_EN bit in QSPI master config register
Change-Id: I2a53c1094b90ac7896e835864848467c52d2a03e Signed-off-by: Roja Rani Yarubandi rojay@codeaurora.org --- M src/soc/qualcomm/sc7280/qspi.c 1 file changed, 10 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/47079/2
Ravi Kumar Bokka has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47079 )
Change subject: HACK sc7280: To support SPI-NOR driver for Rumi ......................................................................
Abandoned
abandon these changes as we used for bringup stage. unfortunately uploaded
-
Ravi kumar (Code Review) -
Ravi Kumar Bokka (Code Review)