Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30990
Change subject: soc/apollolake: Add generation of DMAR table ......................................................................
soc/apollolake: Add generation of DMAR table
Generate DMAR table if VTd feature is enabled.
Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa Signed-off-by: Werner Zeh werner.zeh@siemens.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/systemagent.h M src/soc/intel/common/block/include/intelblocks/p2sb.h 3 files changed, 93 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30990/1
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 0c4ff81..06ebf6c 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. - * Copyright (C) 2017 Siemens AG + * Copyright (C) 2017-2018 Siemens AG * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -20,16 +20,19 @@ #include <arch/acpigen.h> #include <arch/io.h> #include <arch/smp/mpspec.h> +#include <device/pci_ops.h> #include <cbmem.h> #include <cpu/x86/smm.h> #include <gpio.h> #include <intelblocks/acpi.h> #include <intelblocks/pmclib.h> #include <intelblocks/sgx.h> +#include <intelblocks/p2sb.h> #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> #include <soc/pci_devs.h> +#include <soc/systemagent.h> #include <string.h> #include "chip.h"
@@ -178,6 +181,82 @@ fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; }
+static unsigned long soc_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); + uint32_t gfxvtbar = MCHBAR32(GFXVTBAR) & VTBAR_MASK; + uint32_t defvtbar = MCHBAR32(DEFVTBAR) & VTBAR_MASK; + bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; + bool defvten = MCHBAR32(DEFVTBAR) & VTBAR_ENABLED; + unsigned long tmp; + + /* IGD has to be enabled, GFXVTBAR set and enabled as well as allocated + in 32-bit space. */ + if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten + && !MCHBAR32(GFXVTBAR + 4)) { + tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_drhd_fixup(tmp, current); + + /* Add RMRR entry */ + tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + + /* DEFVTBAR has to be set, enabled, and allocated in 32-bit space. */ + if (defvtbar && defvten && !MCHBAR32(DEFVTBAR + 4)) { + tmp = current; + /* + * P2SB may already be hidden. There's no clear rule, when. + * It is needed to get bus, device and function for IOAPIC and + * HPET device which is stored in P2SB device. So unhide it to + * get the info and hide it again when done. + */ + p2sb_unhide(); + struct device *p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); + uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); + uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); + /* Now that it is not needed any more hide P2SB device again. */ + p2sb_hide(); + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, defvtbar); + current += acpi_create_dmar_ds_ioapic(current, + 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); + acpi_dmar_drhd_fixup(tmp, current); + } + + return current; +} + +unsigned long sa_write_acpi_tables(struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + + /* Create DMAR table only if virtualization is enabled */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || + !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED)) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + current = acpi_align_current(current); + + return current; +} + void soc_power_states_generation(int core_id, int cores_per_package) { /* Generate P-state tables */ diff --git a/src/soc/intel/apollolake/include/soc/systemagent.h b/src/soc/intel/apollolake/include/soc/systemagent.h index fe9c15f..55fdccd 100644 --- a/src/soc/intel/apollolake/include/soc/systemagent.h +++ b/src/soc/intel/apollolake/include/soc/systemagent.h @@ -3,6 +3,7 @@ * * Copyright (C) 2015 Intel Corp. * (Written by Andrey Petrov andrey.petrov@intel.com for Intel Corp.) + * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,5 +29,12 @@ #define PCODE_INIT_DONE (1 << 8) #define MCHBAR_RAPL_PPL 0x70A8 #define CORE_DISABLE_MASK 0x7168 +#define CAPID0_A 0xE4 +#define VTD_DISABLE (1 << 23) +#define DEFVTBAR 0x6c80 +#define GFXVTBAR 0x6c88 +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0xfffff000 +#define VTBAR_SIZE 0x1000
#endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index e5c1f3e..22ab140 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,8 +20,10 @@ #include <stddef.h> #include <stdint.h>
-#define PCH_P2SB_E0 0xe0 -#define P2SB_E0_MASKLOCK (1 << 1) +#define PCH_P2SB_E0 0xe0 +#define P2SB_E0_MASKLOCK (1 << 1) +#define PCH_P2SB_IBDF 0x6c +#define PCH_P2SB_HBDF 0x70
enum { P2SB_EP_MASK_0_REG,
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30990 )
Change subject: soc/apollolake: Add generation of DMAR table ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/30990/1/src/soc/intel/apollolake/acpi.c File src/soc/intel/apollolake/acpi.c:
https://review.coreboot.org/#/c/30990/1/src/soc/intel/apollolake/acpi.c@194 PS1, Line 194: in 32-bit space. */ I think the second line of the comment should be two characters to the right.
Hello Patrick Rudolph, Mario Scheithauer, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30990
to look at the new patch set (#2).
Change subject: soc/apollolake: Add generation of DMAR table ......................................................................
soc/apollolake: Add generation of DMAR table
Generate DMAR table if VTd feature is enabled.
Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa Signed-off-by: Werner Zeh werner.zeh@siemens.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/systemagent.h M src/soc/intel/common/block/include/intelblocks/p2sb.h 3 files changed, 93 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30990/2
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30990 )
Change subject: soc/apollolake: Add generation of DMAR table ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30990 )
Change subject: soc/apollolake: Add generation of DMAR table ......................................................................
Patch Set 5: Code-Review+1
(3 comments)
https://review.coreboot.org/#/c/30990/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/30990/5//COMMIT_MSG@7 PS5, Line 7: Add generation of DMAR table Shorter:
Generate DMAR table
https://review.coreboot.org/#/c/30990/5//COMMIT_MSG@10 PS5, Line 10: Tested how?
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c File src/soc/intel/apollolake/acpi.c:
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c@224 PS5, Line 224: /* Now that it is not needed any more hide P2SB device again. */ With the comment above, I believe this comment could be removed.
Hello Patrick Rudolph, Mario Scheithauer, Paul Menzel, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30990
to look at the new patch set (#6).
Change subject: soc/apollolake: Generate DMAR table ......................................................................
soc/apollolake: Generate DMAR table
Generate DMAR table if VTd feature is enabled.
Test=Booted into Linux on mc_apl2 and verified the DMAR table contents. In addition turned off Vtd and verified that no DMAR table is generated at all.
Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa Signed-off-by: Werner Zeh werner.zeh@siemens.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/systemagent.h M src/soc/intel/common/block/include/intelblocks/p2sb.h 3 files changed, 92 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30990/6
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30990 )
Change subject: soc/apollolake: Generate DMAR table ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c File src/soc/intel/apollolake/acpi.c:
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c@194 PS5, Line 194: in 32-bit space. */ The 32-bit limitation was only a workaround for the signature of acpi_create_dmar_drhd(); which uses an uint64_t by now. So it would make more sense to read the full 64-bit register now and don't check for the upper bits to be zero.
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c@247 PS5, Line 247: !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED)) Why only check DEFVTBAR here?
Also, please don't align with the `if` body. Use 4 spaces or 2 tabs.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30990 )
Change subject: soc/apollolake: Generate DMAR table ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c File src/soc/intel/apollolake/acpi.c:
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c@194 PS5, Line 194: in 32-bit space. */
The 32-bit limitation was only a workaround for the […]
Yes, now that you are saying it. So I need to read the complete 64 bit BAR and feed it into acpi_create_dmar_drhd(). Thanks for pointing that out, will change.
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c@247 PS5, Line 247: !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED)) Because if GFX is diasbled (for some reason), VTD can still be active and we need to generate DMAR table. On the other hand, if VTD is disabled, no DMAR table should be generated even if GFX is enabled.
Also, please don't align with the `if` body. Use 4 spaces or 2 tabs.
Sorry, I do not see the issue here. Do you mean the alignment of the second line "!(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED))"? There are two tabs right now.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30990 )
Change subject: soc/apollolake: Generate DMAR table ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c File src/soc/intel/apollolake/acpi.c:
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c@247 PS5, Line 247: !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED))
Because if GFX is diasbled (for some reason), VTD can still be active and we need to generate DMAR t […]
Yes, second line. And I meant indentation relative to the `if`. Currently the second line of the condition aligns with the body (`return current;`). This shouldn't be the case.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30990 )
Change subject: soc/apollolake: Generate DMAR table ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c File src/soc/intel/apollolake/acpi.c:
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c@247 PS5, Line 247: !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED))
Yes, second line. And I meant indentation relative to the `if`. […]
OK, got it. Thank you for explaining, will change.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30990 )
Change subject: soc/apollolake: Generate DMAR table ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c File src/soc/intel/apollolake/acpi.c:
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c@247 PS5, Line 247: !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED))
Because if GFX is diasbled (for some reason), VTD can still be active and we need to generate DMAR table. On the other hand, if VTD is disabled, no DMAR table should be generated even if GFX is enabled.
Right, but you check for `DEFVTBAR & VTBAR_ENABLED` explicitly. Which leaves the case that DEFVTBAR is disable, but VT-d and GFX might be enabled. If would have expected either this:
if (pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) return current;
or this:
if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || (!(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED) && !(MCHBAR32(GFXVTBAR) & VTBAR_ENABLED))) return current;
But still, VT-d is more than just the IOMMUs, so I guess the former makes more sense.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30990 )
Change subject: soc/apollolake: Generate DMAR table ......................................................................
Patch Set 6:
(1 comment)
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c File src/soc/intel/apollolake/acpi.c:
https://review.coreboot.org/#/c/30990/5/src/soc/intel/apollolake/acpi.c@247 PS5, Line 247: !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED))
Because if GFX is diasbled (for some reason), VTD can still be active and we need to generate DMAR […]
Well, I have started exact with the upper code in the first run. Unfortunately, on some steppings of APL an enabled IPU will override the enabled VTD feature inside FSP and disable VTD completely. It will then be the case that CAPID0_A reports an enabled VTD feature while the needed BARs will be disabled and locked. In this case there will be the header of the DMAR generated while the content will be missing. Therefore I have added the check for at least enabled DEFVTBAR, in which case VTD is available at all on the system. I will add a description in the comment to clarify this.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30990 )
Change subject: soc/apollolake: Generate DMAR table ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/30990/6/src/soc/intel/apollolake/include/soc... File src/soc/intel/apollolake/include/soc/systemagent.h:
https://review.coreboot.org/#/c/30990/6/src/soc/intel/apollolake/include/soc... PS6, Line 37: #define VTBAR_MASK 0xfffff000 This should be extended to support the full 64-bit (actually 40-bit) value. e.g. `0xfffffff000ull` or `(~0xfffull)`
Hello Patrick Rudolph, Mario Scheithauer, Paul Menzel, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30990
to look at the new patch set (#7).
Change subject: soc/apollolake: Generate DMAR table ......................................................................
soc/apollolake: Generate DMAR table
Generate DMAR table if VTd feature is enabled.
Test=Booted into Linux on mc_apl2 and verified the DMAR table contents. In addition turned off Vtd and verified that no DMAR table is generated at all.
Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa Signed-off-by: Werner Zeh werner.zeh@siemens.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/systemagent.h M src/soc/intel/common/block/include/intelblocks/p2sb.h M src/soc/intel/common/block/include/intelblocks/systemagent.h 4 files changed, 100 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30990/7
Hello Patrick Rudolph, Mario Scheithauer, Paul Menzel, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30990
to look at the new patch set (#8).
Change subject: soc/apollolake: Generate DMAR table ......................................................................
soc/apollolake: Generate DMAR table
Generate DMAR table if VTd feature is enabled.
Test=Booted into Linux on mc_apl2 and verified the DMAR table contents. In addition turned off Vtd and verified that no DMAR table is generated at all.
Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa Signed-off-by: Werner Zeh werner.zeh@siemens.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/systemagent.h M src/soc/intel/common/block/include/intelblocks/p2sb.h M src/soc/intel/common/block/include/intelblocks/systemagent.h 4 files changed, 100 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30990/8
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30990 )
Change subject: soc/apollolake: Generate DMAR table ......................................................................
Patch Set 8: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30990 )
Change subject: soc/apollolake: Generate DMAR table ......................................................................
soc/apollolake: Generate DMAR table
Generate DMAR table if VTd feature is enabled.
Test=Booted into Linux on mc_apl2 and verified the DMAR table contents. In addition turned off Vtd and verified that no DMAR table is generated at all.
Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa Signed-off-by: Werner Zeh werner.zeh@siemens.com Reviewed-on: https://review.coreboot.org/c/30990 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/systemagent.h M src/soc/intel/common/block/include/intelblocks/p2sb.h M src/soc/intel/common/block/include/intelblocks/systemagent.h 4 files changed, 100 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 0c4ff81..6780ec4 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. - * Copyright (C) 2017 Siemens AG + * Copyright (C) 2017-2019 Siemens AG * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -20,16 +20,19 @@ #include <arch/acpigen.h> #include <arch/io.h> #include <arch/smp/mpspec.h> +#include <device/pci_ops.h> #include <cbmem.h> #include <cpu/x86/smm.h> #include <gpio.h> #include <intelblocks/acpi.h> #include <intelblocks/pmclib.h> #include <intelblocks/sgx.h> +#include <intelblocks/p2sb.h> #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> #include <soc/pci_devs.h> +#include <soc/systemagent.h> #include <string.h> #include "chip.h"
@@ -178,6 +181,88 @@ fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; }
+static unsigned long soc_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); + uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; + uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK; + bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; + bool defvten = MCHBAR32(DEFVTBAR) & VTBAR_ENABLED; + unsigned long tmp; + + /* IGD has to be enabled, GFXVTBAR set and enabled. */ + if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { + tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_drhd_fixup(tmp, current); + + /* Add RMRR entry */ + tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + + /* DEFVTBAR has to be set and enabled. */ + if (defvtbar && defvten) { + tmp = current; + /* + * P2SB may already be hidden. There's no clear rule, when. + * It is needed to get bus, device and function for IOAPIC and + * HPET device which is stored in P2SB device. So unhide it to + * get the info and hide it again when done. + */ + p2sb_unhide(); + struct device *p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); + uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); + uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); + p2sb_hide(); + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, defvtbar); + current += acpi_create_dmar_ds_ioapic(current, + 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); + acpi_dmar_drhd_fixup(tmp, current); + } + + return current; +} + +unsigned long sa_write_acpi_tables(struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + + /* Create DMAR table only if virtualization is enabled. Due to some + * constraints on Apollo Lake SoC (some stepping affected), VTD could + * not be enabled together with IPU. Doing so will override and disable + * VTD while leaving CAPID0_A still reporting that VTD is available. + * As in this case FSP will lock VTD to disabled state, we need to make + * sure that DMAR table generation only happens when at least DEFVTBAR + * is enabled. Otherwise the DMAR header will be generated while the + * content of the table will be missing. + */ + + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || + !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED)) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + current = acpi_align_current(current); + + return current; +} + void soc_power_states_generation(int core_id, int cores_per_package) { /* Generate P-state tables */ diff --git a/src/soc/intel/apollolake/include/soc/systemagent.h b/src/soc/intel/apollolake/include/soc/systemagent.h index fe9c15f..46c1d7d 100644 --- a/src/soc/intel/apollolake/include/soc/systemagent.h +++ b/src/soc/intel/apollolake/include/soc/systemagent.h @@ -3,6 +3,7 @@ * * Copyright (C) 2015 Intel Corp. * (Written by Andrey Petrov andrey.petrov@intel.com for Intel Corp.) + * Copyright (C) 2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,5 +29,12 @@ #define PCODE_INIT_DONE (1 << 8) #define MCHBAR_RAPL_PPL 0x70A8 #define CORE_DISABLE_MASK 0x7168 +#define CAPID0_A 0xE4 +#define VTD_DISABLE (1 << 23) +#define DEFVTBAR 0x6c80 +#define GFXVTBAR 0x6c88 +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0xfffffff000ull +#define VTBAR_SIZE 0x1000
#endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index e5c1f3e..72a3a33 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,8 +20,10 @@ #include <stddef.h> #include <stdint.h>
-#define PCH_P2SB_E0 0xe0 -#define P2SB_E0_MASKLOCK (1 << 1) +#define PCH_P2SB_E0 0xe0 +#define P2SB_E0_MASKLOCK (1 << 1) +#define PCH_P2SB_IBDF 0x6c +#define PCH_P2SB_HBDF 0x70
enum { P2SB_EP_MASK_0_REG, diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index babf9ce..133047c 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -33,6 +33,7 @@ #define MCHBAR8(x) (*(volatile u8 *)(MCH_BASE_ADDRESS + x)) #define MCHBAR16(x) (*(volatile u16 *)(MCH_BASE_ADDRESS + x)) #define MCHBAR32(x) (*(volatile u32 *)(MCH_BASE_ADDRESS + x)) +#define MCHBAR64(x) (*(volatile u64 *)(MCH_BASE_ADDRESS + x))
/* Perform System Agent Initialization during Bootblock phase */ void bootblock_systemagent_early_init(void);
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