Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73392 )
Change subject: [WIP]mb/ibm: Add IBM SBP1 ......................................................................
[WIP]mb/ibm: Add IBM SBP1
The IBM SBP1 is an evaluation platform.
It's utilising: - 4 SPR sockets, having 16 DIMMs each - 32x CPU PCIe slots - 2x M.2 PCH PCIe slots - Dual 200Gbit/s NIC - SPI TPM
It has an AST2600 BMC for remote managment.
It doesn't have: - External facing USB ports - Video outputs
*Needs additional patches to be upstreamed.*
Test: The board boots to Linux with all 384 cores available. All PCI devices are working and no errors in ACPI.
Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 --- A src/mainboard/ibm/Kconfig A src/mainboard/ibm/Kconfig.name A src/mainboard/ibm/sbp1/Kconfig A src/mainboard/ibm/sbp1/Kconfig.name A src/mainboard/ibm/sbp1/Makefile.inc A src/mainboard/ibm/sbp1/acpi/platform.asl A src/mainboard/ibm/sbp1/board.fmd A src/mainboard/ibm/sbp1/board_info.txt A src/mainboard/ibm/sbp1/bootblock.c A src/mainboard/ibm/sbp1/devicetree.cb A src/mainboard/ibm/sbp1/dsdt.asl A src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h A src/mainboard/ibm/sbp1/ramstage.c A src/mainboard/ibm/sbp1/romstage.c 14 files changed, 980 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/73392/1
diff --git a/src/mainboard/ibm/Kconfig b/src/mainboard/ibm/Kconfig new file mode 100644 index 0000000..5553fbf --- /dev/null +++ b/src/mainboard/ibm/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_IBM + +choice + prompt "Mainboard model" + +source "src/mainboard/ibm/*/Kconfig.name" + +endchoice + +source "src/mainboard/ibm/*/Kconfig" + +config MAINBOARD_VENDOR + default "IBM" + +endif # VENDOR_IBM diff --git a/src/mainboard/ibm/Kconfig.name b/src/mainboard/ibm/Kconfig.name new file mode 100644 index 0000000..7f3cb17 --- /dev/null +++ b/src/mainboard/ibm/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_IBM + bool "IBM" diff --git a/src/mainboard/ibm/sbp1/Kconfig b/src/mainboard/ibm/sbp1/Kconfig new file mode 100644 index 0000000..7c94817 --- /dev/null +++ b/src/mainboard/ibm/sbp1/Kconfig @@ -0,0 +1,44 @@ +if BOARD_IBM_SBP1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select IPMI_KCS + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select MAINBOARD_USES_FSP2_0 + select SOC_INTEL_SAPPHIRERAPID_SP + select SUPERIO_ASPEED_AST2400 # Check if AST2400 is compatible + select HAVE_ACPI_TABLES + select MAINBOARD_USES_IFD_GBE_REGION + select VPD + select DEFAULT_X2APIC + +config MAINBOARD_DIR + string + default "ibm/sbp1" + +config MAINBOARD_PART_NUMBER + string + default "SBP1" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config MAX_SOCKET + int + default 4 + +config MAX_SOCKET_UPD + int + default 4 + +config MAX_CPUS + int + default 384 + +config DEBUG_SMI + default y + +endif diff --git a/src/mainboard/ibm/sbp1/Kconfig.name b/src/mainboard/ibm/sbp1/Kconfig.name new file mode 100644 index 0000000..fec27e6 --- /dev/null +++ b/src/mainboard/ibm/sbp1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_IBM_SBP1 + bool "SBP1" diff --git a/src/mainboard/ibm/sbp1/Makefile.inc b/src/mainboard/ibm/sbp1/Makefile.inc new file mode 100644 index 0000000..0688aa1 --- /dev/null +++ b/src/mainboard/ibm/sbp1/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += bootblock.c +romstage-y += romstage.c +ramstage-y += ramstage.c +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/ibm/sbp1/acpi/platform.asl b/src/mainboard/ibm/sbp1/acpi/platform.asl new file mode 100644 index 0000000..afb4cf7 --- /dev/null +++ b/src/mainboard/ibm/sbp1/acpi/platform.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> + +Name (_S0, Package () // mandatory system state +{ + 0x00, 0x00, 0x00, 0x00 +}) + +Name (_S5, Package () // mandatory system state +{ + 0x07, 0x00, 0x00, 0x00 +}) + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/ibm/sbp1/board.fmd b/src/mainboard/ibm/sbp1/board.fmd new file mode 100644 index 0000000..708d4b2 --- /dev/null +++ b/src/mainboard/ibm/sbp1/board.fmd @@ -0,0 +1,11 @@ +FLASH@0xfc000000 64M { + SI_ALL@0x0 0x03000000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x2fff000 + } + RW_MRC_CACHE@0x3000000 0x10000 + FMAP 0x800 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + COREBOOT(CBFS) +} diff --git a/src/mainboard/ibm/sbp1/board_info.txt b/src/mainboard/ibm/sbp1/board_info.txt new file mode 100644 index 0000000..8510954 --- /dev/null +++ b/src/mainboard/ibm/sbp1/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: IBM +Board name: SBP1 +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/ibm/sbp1/bootblock.c b/src/mainboard/ibm/sbp1/bootblock.c new file mode 100644 index 0000000..b7edef0 --- /dev/null +++ b/src/mainboard/ibm/sbp1/bootblock.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define ASPEED_SIO_PORT 0x2E +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +void bootblock_mainboard_early_init(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPU uses two of AST2600 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + * For ArcherCity CRB, only SUART1 is used. + */ + uint16_t lpciod = LPC_IOD_COMA_RANGE; + uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMA_EN); + + /* Open IO windows: 0x3f8 for com1 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod); + /* LPC I/O enable: com1 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe); + + /* Enable com1 (0x3f8) and superio (0x2e) */ + pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod); + pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe); + + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/ibm/sbp1/devicetree.cb b/src/mainboard/ibm/sbp1/devicetree.cb new file mode 100644 index 0000000..62f48c0 --- /dev/null +++ b/src/mainboard/ibm/sbp1/devicetree.cb @@ -0,0 +1,117 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/spr + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # configure device interrupt routing + register "ir00_routing" = "0x3210" # IR00, Dev31 + register "ir01_routing" = "0x3210" # IR01, Dev30 + register "ir02_routing" = "0x3210" # IR02, Dev29 + register "ir03_routing" = "0x3210" # IR03, Dev28 + register "ir04_routing" = "0x3210" # IR04, Dev27 + + # configure interrupt polarity control + register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow + register "ipc1" = "0x00000000" # IPC1 + register "ipc2" = "0x00000000" # IPC2 + register "ipc3" = "0x00000000" # IPC3 + + # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs + register "turbo_ratio_limit" = "0x181819191e242424" + register "turbo_ratio_limit_cores" = "0x3836322e2a1c1a18" + + # configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL + register "pstate_req_ratio" = "0xa" + + # configure VT-d + register "vtd_support" = "1" + register "x2apic" = "1" + + register "gen1_dec" = "0x000c0ca1" # IPMI KCS + + register "cstate_states" = "CSTATES_C1C6" + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Intel device 09a2: Memory Map/Intel VT-d + device pci 00.1 on end # Intel device 09a4: Mesh to IAL + device pci 00.4 on end # Intel device 0b23: IEH + device pci 00.2 on end # Intel device 09a3: RAS + device pci 01.0 on end # Intel device 3c01: Port A PCIe Gen5 + device pci 02.0 on end # Intel device 3c01: Port D PCIe Gen4 + device pci 03.0 on end # Intel device 3c01: Port B PCIe Gen5 + device pci 04.0 on end # Intel device 3c01: Port C PCIe Gen4 + device pci 05.0 on end # Intel device 3c01: Port C PCIe Gen5 + device pci 06.0 on end # Intel device 3c01: Port B PCIe Gen4 + device pci 07.0 on end # Intel device 3c01: Port D PCIe Gen5 + device pci 08.0 on end # Intel device 2020: DMI + device pci 09.0 on end # Intel device 1bb9: PCH PCIe Root Port #1 + device pci 0a.0 on end # Intel device 1bba: PCH PCIe Root Port #2 + device pci 0b.0 on end # Intel device 1bbb: PCH PCIe Root Port #3 + device pci 0c.0 on end # Intel device 1bbc: PCH PCIe Root Port #4 + device pci 0d.0 on end # Intel device 1bbd: PCH PCIe Root Port #5 + device pci 0e.0 on end # Intel device 1bbe: PCH PCIe Root Port #6 + device pci 0f.0 on end # Intel device 1bbf: PCH PCIe Root Port #7 + device pci 10.0 on end # Intel device 1bb0: PCH PCIe Root Port #8 + device pci 11.0 on end # Intel device 1bb1: PCH PCIe Root Port #9 + device pci 12.0 on end # Intel device 1bb2: PCH PCIe Root Port #10 + device pci 13.0 on end # Intel device 1bb3: PCH PCIe Root Port #11 + device pci 14.0 on end # Intel device 1bcd: PCH USB 3.0 XHCI Controller + device pci 14.2 on end # Intel device 1bce: PCH PMC shared RAM + device pci 15.0 on end # Intel device 1bff + device pci 16.0 on end # Intel device 1be0: PCH ME HECI #1 + device pci 16.1 on end # Intel device 1be1: PCH ME HECI #2 + device pci 16.3 off end # Serial controller: Intel Corporation Device 1be3 + device pci 16.4 on end # Intel device 1be4: PCH ME HECI #3 + device pci 16.5 on end # Intel device 1be5: PCH ME HECI #4 + device pci 16.6 on end # Intel device 1be6 + device pci 17.0 on end # Intel device 1ba2: PCH SATA controller 0 (AHCI) + device pci 18.0 on end # Intel device 1bf2: PCH SATA controller 1 (AHCI) + device pci 19.0 off end # Intel device 1bd2: PCH SATA controller 2 (AHCI) + device pci 1a.0 on end # Intel device 1bb4: PCH PCIe Root Port #12 + device pci 1b.0 on end # Intel device 1bb5: PCH PCIe Root Port #13 + device pci 1e.0 off end # Intel device Communication controller: Intel Corporation Device 1bad + + device pci 1f.0 on # Intel device 1b81: PCH eSPI controller + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + end + chip drivers/ipmi # BMC KCS + device pnp ca2.0 on end + register "bmc_i2c_address" = "0x20" + register "bmc_boot_timeout" = "60" + end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end + end + device pci 1f.1 on end # Intel device 1bc6: PCH P2SB + device pci 1f.2 on end # Intel device 1bc7: PCH PMC + device pci 1f.3 off end # Intel device 1bc8: PCH audio + device pci 1f.4 on end # Intel device 1bc9: PCH SMBus + device pci 1f.5 on end # Intel device 1bca: PCH SPI controller + device pci 1f.6 off end # Intel device 1bcb: PCH GbE controller + device pci 1f.7 on end # Intel device 1bcc: PCH TH + + end +end diff --git a/src/mainboard/ibm/sbp1/dsdt.asl b/src/mainboard/ibm/sbp1/dsdt.asl new file mode 100644 index 0000000..42e4b89 --- /dev/null +++ b/src/mainboard/ibm/sbp1/dsdt.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + // platform ACPI tables + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + // SPR-SP ACPI tables + #include <soc/intel/xeon_sp/spr/acpi/uncore.asl> + + // LPC related entries + Scope (_SB.PC00) + { + #include <soc/intel/xeon_sp/spr/acpi/pch.asl> + } + + // FIXME: Drop on rebase + Name (AHPE, 0) + Name (IO80, 0) +} diff --git a/src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h b/src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h new file mode 100644 index 0000000..c5ceec9 --- /dev/null +++ b/src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + /* ------- GPIO Group GPPC_A ------- */ + /* PCH default for ESPI inter GPPC_A0-A9 */ + /* Unused */ + PAD_NC(GPPC_A10, NONE), + PAD_NC(GPPC_A11, NONE), + PAD_NC(GPPC_A12, NONE), + PAD_NC(GPPC_A13, NONE), + PAD_NC(GPPC_A14, NONE), + PAD_NC(GPPC_A15, NONE), + PAD_NC(GPPC_A16, NONE), + PAD_NC(GPPC_A17, NONE), + PAD_NC(GPPC_A18, NONE), + PAD_NC(GPPC_A19, NONE), + + /* ------- GPIO Group GPPC_B ------- */ + /* PTI */ + PAD_CFG_NF(GPPC_B0, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B1, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B2, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B3, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B4, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B5, NONE, DEEP, NF4), + /* GPPC_B12-B23 - PTI */ + PAD_CFG_NF(GPPC_B12, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B13, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B14, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B15, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B16, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B17, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B18, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B19, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B20, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B21, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B22, NONE, DEEP, NF4), + PAD_CFG_NF(GPPC_B23, NONE, DEEP, NF4), + /* USB2_OC1_N */ + PAD_NC(GPPC_B6, NONE), + /* USB2_OC2_N */ + PAD_NC(GPPC_B7, NONE), + /* USB2_OC3_N */ + PAD_NC(GPPC_B8, NONE), + /* USB2_OC4_N */ + PAD_NC(GPPC_B9, NONE), + /* USB2_OC5_N */ + PAD_NC(GPPC_B10, NONE), + /* USB2_OC6_N */ + PAD_NC(GPPC_B11, NONE), + + /* ------- GPIO Community 1 ------- */ + /* ------- GPIO Group GPPC_C ------- */ + /* ME_SML0CLK */ + PAD_CFG_NF(GPPC_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPPC_C1, NONE, DEEP, NF1), + PAD_CFG_NF(GPPC_C2, NONE, DEEP, NF1), + + /* FM_BIOS_POST_CMPLT_N */ + PAD_CFG_GPO(GPPC_C17, 1, DEEP), + + /* No Connect */ + PAD_NC(GPPC_C3, NONE), + PAD_NC(GPPC_C4, NONE), + PAD_NC(GPPC_C5, NONE), + PAD_NC(GPPC_C6, NONE), + PAD_NC(GPPC_C7, NONE), + PAD_NC(GPPC_C8, NONE), + PAD_NC(GPPC_C9, NONE), + PAD_NC(GPPC_C10, NONE), + PAD_NC(GPPC_C11, NONE), + PAD_NC(GPPC_C12, NONE), + PAD_NC(GPPC_C13, NONE), + PAD_NC(GPPC_C14, NONE), + PAD_NC(GPPC_C15, NONE), + PAD_NC(GPPC_C16, NONE), + PAD_NC(GPPC_C18, NONE), + PAD_NC(GPPC_C19, NONE), + PAD_NC(GPPC_C20, NONE), + PAD_NC(GPPC_C21, NONE), + + /* ------- GPIO Group GPPC_S ------- */ + PAD_NC(GPPC_S0, NONE), + PAD_NC(GPPC_S1, NONE), + PAD_NC(GPPC_S2, NONE), + PAD_NC(GPPC_S3, NONE), + PAD_NC(GPPC_S4, NONE), + PAD_NC(GPPC_S5, NONE), + PAD_NC(GPPC_S6, NONE), + PAD_NC(GPPC_S7, NONE), + PAD_NC(GPPC_S8, NONE), + PAD_NC(GPPC_S10, NONE), + PAD_NC(GPPC_S11, NONE), + + /* FM_SMI_ACTIVE_N */ + PAD_CFG_NF(GPPC_S9, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_D ------- */ + /* SMB_HOST_STBY_BMC_LVC3_R2 */ + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + /* PLTRST PCHHOT_N */ + //PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), + //PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), + + /* No Connect */ + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Community 2 ------- */ + /* ------- GPIO Group GPP_O ------- */ + /* Unused */ + PAD_NC(GPP_O0, NONE), + PAD_NC(GPP_O7, NONE), + + /* ------- GPIO Community 3 ------- */ + /* ------- GPIO Group GPP_E ------- */ + /* Unused */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E6, NONE), + PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E14, NONE), + PAD_NC(GPP_E17, NONE), + PAD_NC(GPP_E18, NONE), + PAD_NC(GPP_E19, NONE), + + /* SS2/SS1 SATA/PCIE gpio */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* SSD2/SSD1 DEVSLP */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF2), + + PAD_CFG_GPI(GPP_E15, NONE, DEEP), + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + + /* ------- GPIO Community 4 ------- */ + /* -------- GPIO Group GPPC_H -------- */ + /* Unused */ + PAD_NC(GPPC_H0, NONE), + PAD_NC(GPPC_H1, NONE), + PAD_NC(GPPC_H6, NONE), + PAD_NC(GPPC_H7, NONE), + PAD_NC(GPPC_H15, NONE), + PAD_NC(GPPC_H16, NONE), + PAD_NC(GPPC_H17, NONE), + PAD_NC(GPPC_H18, NONE), + PAD_NC(GPPC_H19, NONE), + + /* ------- GPIO Group GPP_J ------- */ + /* Use PCH defaults */ + /* GPP_J0 CPUPWRGD */ + /* GPP_J1 CPU_THRMTRIP_N */ + /* GPP_J2 PLTRST_CPU_N */ + /* GPP_J3 TRIGGER0_N */ + /* GPP_J4 TRIGGER1_N */ + /* GPP_J5 CPU_PWER_DEBUG_N */ + /* GPP_J6 CPU_MEMTRIP_N */ + /* GPP_J7 CPU_MSMI_N */ + /* GPP_J12 CPU_ERR0_N */ + /* GPP_J13 CPU_CATERR_N */ + /* GPP_J14 CPU_ERR1_N */ + /* GPP_J15 CPU_ERR2_N */ + + /* ------- GPIO Community 5 ------- */ + /* ------- GPIO Group GPP_I ------- */ + /* Unused */ + PAD_NC(GPP_I12, NONE), + PAD_NC(GPP_I13, NONE), + PAD_NC(GPP_I14, NONE), + PAD_NC(GPP_I15, NONE), + PAD_NC(GPP_I16, NONE), + PAD_NC(GPP_I17, NONE), + PAD_NC(GPP_I22, NONE), + PAD_NC(GPP_I23, NONE), + /* SPI TPM IRQ */ + PAD_CFG_GPI(GPP_I17, NONE, DEEP), + + /* ------- GPIO Group GPP_L ------- */ + /* Chip default */ + /* GPP_L_0 PM_SYNC_0 */ + /* GPP_L_1 PM_DOWN_0 */ + + /* Unused */ + PAD_NC(GPP_L3, NONE), + PAD_NC(GPP_L4, NONE), + /* FM_PASSWORD_CLEAR_N */ + PAD_NC(GPP_L5, NONE), + PAD_NC(GPP_L6, NONE), + PAD_NC(GPP_L7, NONE), + PAD_NC(GPP_L8, NONE), + + /* ------- GPIO Group GPP_M ------- */ + /* Unused */ + PAD_NC(GPP_M0, NONE), + PAD_NC(GPP_M1, NONE), + PAD_NC(GPP_M2, NONE), + PAD_NC(GPP_M3, NONE), + PAD_NC(GPP_M4, NONE), + PAD_NC(GPP_M5, NONE), + PAD_NC(GPP_M6, NONE), + PAD_NC(GPP_M7, NONE), + PAD_NC(GPP_M8, NONE), + PAD_NC(GPP_M11, NONE), + PAD_NC(GPP_M12, NONE), + PAD_NC(GPP_M15, NONE), + PAD_NC(GPP_M16, NONE), + PAD_NC(GPP_M17, NONE), + + /* ------- GPIO Group GPP_N ------- */ + /* Unused */ + PAD_NC(GPP_N1, NONE), + PAD_NC(GPP_N4, NONE), +}; + +static const struct pad_config override_fsp_gpio_table[] = { + PAD_CFG_GPI_TRIG_OWN(GPPC_B6, NONE, DEEP, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_D22, \ + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_RX_STATE | \ + PAD_TRIG(OFF) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ + PAD_PULL(NONE) | PAD_CFG_OWN_GPIO(ACPI)), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/ibm/sbp1/ramstage.c b/src/mainboard/ibm/sbp1/ramstage.c new file mode 100644 index 0000000..11d0a8b --- /dev/null +++ b/src/mainboard/ibm/sbp1/ramstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +#include "include/spr_sbp1_gpio.h" + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + /* configure Emmitsburg PCH GPIO controller after FSP-M */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/ibm/sbp1/romstage.c b/src/mainboard/ibm/sbp1/romstage.c new file mode 100644 index 0000000..bcbf9bf --- /dev/null +++ b/src/mainboard/ibm/sbp1/romstage.c @@ -0,0 +1,386 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <drivers/vpd/vpd.h> +#include <drivers/ocp/include/vpd.h> +#include <soc/romstage.h> +#include <defs_cxl.h> +#include <defs_iio.h> + +/* For now only set 3 fields and hard-coded others, should be extended in the future */ +#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \ + { \ + .SLOTEIP = 0, \ + .SLOTHPCAP = slotimp, \ + .SLOTHPSUP = slotimp, \ + .SLOTPIP = 0, \ + .SLOTAIP = 0, \ + .SLOTMRLSP = 0, \ + .SLOTPCP = 0, \ + .SLOTABP = 0, \ + .SLOTIMP = slotimp, \ + .SLOTSPLS = 0, \ + .SLOTSPLV = slotimp ? 25 : 0, \ + .SLOTPSP = slotpsp, \ + .VppEnabled = 0, \ + .VppPort = 0, \ + .VppAddress = 0, \ + .MuxAddress = 0, \ + .ChannelID = 0, \ + .PciePortEnable = !pexphide, \ + .PEXPHIDE = pexphide, \ + .HidePEXPMenu = pexphide, \ + .PciePortOwnership = 0, \ + .RetimerConnectCount = 0, \ + .PcieMaxPayload = 0x7, \ + .PcieHotPlugOnPort = slotimp, \ + } + +#define IIO_PORT_SETTINGS (1 + 5 * 8) + +struct sbp1_iio_socket_config { + UPD_IIO_PCIE_PORT_CONFIG_ENTRY port_config[IIO_PORT_SETTINGS]; +}; + +static const struct sbp1_iio_socket_config +sbp1_socket_config[CONFIG_MAX_SOCKET] = { +{ + { + /* DMI port: array index 0 */ + CFG_UPD_PCIE_PORT(0, 0, 0), + /* IOU0 (PE0): array index 1 ~ 8 Not Used */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU1 (PE1): array index 9 ~ 16 IIO_BIFURCATE_x4x4x4x4 */ + CFG_UPD_PCIE_PORT(0, 1, 12), /* 26:01.0 RSSD12 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 11), /* 26:03.0 RSSD11 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 10), /* 26:05.0 RSSD10 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 9), /* 26:07.0 RSSD09 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */ + CFG_UPD_PCIE_PORT(0, 1, 13), /* 37:01.0 RSSD13 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 14), /* 37:03.0 RSSD14 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 15), /* 37:05.0 RSSD15 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 16), /* 37:07.0 RSSD16 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU3 (PE3): array index 25 ~ 32 IIO_BIFURCATE_x4x4x4x4 */ + CFG_UPD_PCIE_PORT(0, 0, 0), /* 48:01.0 - NIC2*/ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 0, 0), /* 48:05.0 - NIC1 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU4 (PE4): array index 33 ~ 40 Not Used */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + } +}, +{ + { + /* DMI port: array index 0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU0 (PE0): array index 1 ~ 8 Not Used */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU1 (PE1): array index 9 ~ 16 IIO_BIFURCATE_x4x4x4x4 */ + CFG_UPD_PCIE_PORT(0, 1, 28), /* 26:01.0 RSSD28 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 27), /* 26:03.0 RSSD27 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 26), /* 26:05.0 RSSD26 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 25), /* 26:07.0 RSSD25 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */ + CFG_UPD_PCIE_PORT(0, 1, 29), /* 37:01.0 RSSD29 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 30), /* 37:03.0 RSSD30 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 31), /* 37:05.0 RSSD31 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 32), /* 37:07.0 RSSD32 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU3 (PE3): array index 25 ~ 32 Not used */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU4 (PE4): array index 33 ~ 40 IIO_BIFURCATE_x4x4x4x4 */ + CFG_UPD_PCIE_PORT(0, 0, 0), /* 59:01.0 - NIC2 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 0, 0), /* 59:05.0 - NIC1 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + } +}, +{ + { + /* DMI port: array index 0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU0 (PE0): array index 1 ~ 8 Not Used */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU1 (PE1): array index 9 ~ 16 Not used */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */ + CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:01.0 - NIC1 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:05.0 - NIC2 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU3 (PE3): array index 25 ~ 32 IIO_BIFURCATE_x4x4x4x4 */ + CFG_UPD_PCIE_PORT(0, 1, 17), /* 48:01.0 - RSSD17 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 18), /* 48:03.0 - RSSD18 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 19), /* 48:05.0 - RSSD19 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 20), /* 48:07.0 - RSSD20 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU4 (PE4): array index 33 ~ 40 IIO_BIFURCATE_x4x4x4x4 */ + CFG_UPD_PCIE_PORT(0, 1, 24), /* 59:01.0 - RSSD24 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 23), /* 59:03.0 - RSSD23*/ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 22), /* 59:05.0 - RSSD22 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 21), /* 59:07.0 - RSSD21 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + } +}, +{ + { + /* DMI port: array index 0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU0 (PE0): array index 1 ~ 8 Not Used */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU1 (PE1): array index 9 ~ 16 Not used */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */ + CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:01.0 - NIC1 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:05.0 - NIC2 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU3 (PE3): array index 25 ~ 32 IIO_BIFURCATE_x4x4x4x4 */ + CFG_UPD_PCIE_PORT(0, 1, 1), /* 48:01.0 - RSSD01 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 2), /* 48:03.0 - RSSD02 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 3), /* 48:05.0 - RSSD03 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 4), /* 48:07.0 - RSSD04 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU4 (PE4): array index 33 ~ 40 IIO_BIFURCATE_x4x4x4x4 */ + CFG_UPD_PCIE_PORT(0, 1, 8), /* 59:01.0 - RSSD08 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 7), /* 59:03.0 - RSSD07*/ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 6), /* 59:05.0 - RSSD06 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 5), /* 59:07.0 - RSSD05 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + } +}, +}; +static UPD_IIO_PCIE_PORT_CONFIG iio_bifur_table[CONFIG_MAX_SOCKET] = {0}; +static UINT8 deemphasis_list[CONFIG_MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET]; + +static void mainboard_config_iio(FSPM_UPD *mupd) +{ + UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig; + int port, socket; + + mupd->FspmConfig.IioPcieConfigTablePtr = (UINT32) iio_bifur_table; + mupd->FspmConfig.IioPcieConfigTableNumber = CONFIG_MAX_SOCKET; + + for (socket = 0; socket < CONFIG_MAX_SOCKET; socket++) { + PciePortConfig = &iio_bifur_table[socket]; + + /* Array sbp1_socket_config only configures DMI, IOU0 ~ IOU4, the rest will be left zero */ + for (port = 0; port < IIO_PORT_SETTINGS; port++) { + PciePortConfig->SLOTIMP[port] = sbp1_socket_config[socket].port_config[port].SLOTIMP; + PciePortConfig->SLOTPSP[port] = sbp1_socket_config[socket].port_config[port].SLOTPSP; + PciePortConfig->SLOTHPCAP[port] = sbp1_socket_config[socket].port_config[port].SLOTHPCAP; + PciePortConfig->SLOTHPSUP[port] = sbp1_socket_config[socket].port_config[port].SLOTHPSUP; + PciePortConfig->SLOTSPLS[port] = sbp1_socket_config[socket].port_config[port].SLOTSPLS; + PciePortConfig->SLOTSPLV[port] = sbp1_socket_config[socket].port_config[port].SLOTSPLV; + PciePortConfig->VppAddress[port] = sbp1_socket_config[socket].port_config[port].VppAddress; + PciePortConfig->SLOTPIP[port] = sbp1_socket_config[socket].port_config[port].SLOTPIP; + PciePortConfig->SLOTAIP[port] = sbp1_socket_config[socket].port_config[port].SLOTAIP; + PciePortConfig->SLOTMRLSP[port] = sbp1_socket_config[socket].port_config[port].SLOTMRLSP; + PciePortConfig->SLOTPCP[port] = sbp1_socket_config[socket].port_config[port].SLOTPCP; + PciePortConfig->SLOTABP[port] = sbp1_socket_config[socket].port_config[port].SLOTABP; + PciePortConfig->VppEnabled[port] = sbp1_socket_config[socket].port_config[port].VppEnabled; + PciePortConfig->VppPort[port] = sbp1_socket_config[socket].port_config[port].VppPort; + PciePortConfig->MuxAddress[port] = sbp1_socket_config[socket].port_config[port].MuxAddress; + PciePortConfig->PciePortEnable[port] = sbp1_socket_config[socket].port_config[port].PciePortEnable; + PciePortConfig->PEXPHIDE[port] = sbp1_socket_config[socket].port_config[port].PEXPHIDE; + PciePortConfig->PcieHotPlugOnPort[port] = sbp1_socket_config[socket].port_config[port].PcieHotPlugOnPort; + PciePortConfig->PcieMaxPayload[port] = sbp1_socket_config[socket].port_config[port].PcieMaxPayload; + } + + /* Socket0: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ + for (port = IIO_PORT_SETTINGS; port < MAX_IIO_PORTS_PER_SOCKET; port++) { + PciePortConfig->PEXPHIDE[port] = 1; + PciePortConfig->HidePEXPMenu[port] = 1; + } + } + + iio_bifur_table[0].ConfigIOU[0] = IIO_BIFURCATE_xxxxxxxx; + iio_bifur_table[0].ConfigIOU[1] = IIO_BIFURCATE_x4x4x4x4; + iio_bifur_table[0].ConfigIOU[2] = IIO_BIFURCATE_x4x4x4x4; + iio_bifur_table[0].ConfigIOU[3] = IIO_BIFURCATE_x4x4x4x4; + iio_bifur_table[0].ConfigIOU[4] = IIO_BIFURCATE_xxxxxxxx; + + iio_bifur_table[1].ConfigIOU[0] = IIO_BIFURCATE_xxxxxxxx; + iio_bifur_table[1].ConfigIOU[1] = IIO_BIFURCATE_x4x4x4x4; + iio_bifur_table[1].ConfigIOU[2] = IIO_BIFURCATE_x4x4x4x4; + iio_bifur_table[1].ConfigIOU[3] = IIO_BIFURCATE_xxxxxxxx; + iio_bifur_table[1].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4; + + iio_bifur_table[2].ConfigIOU[0] = IIO_BIFURCATE_xxxxxxxx; + iio_bifur_table[2].ConfigIOU[1] = IIO_BIFURCATE_xxxxxxxx; + iio_bifur_table[2].ConfigIOU[2] = IIO_BIFURCATE_x4x4x4x4; + iio_bifur_table[2].ConfigIOU[3] = IIO_BIFURCATE_x4x4x4x4; + iio_bifur_table[2].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4; + + iio_bifur_table[3].ConfigIOU[0] = IIO_BIFURCATE_xxxxxxxx; + iio_bifur_table[3].ConfigIOU[1] = IIO_BIFURCATE_xxxxxxxx; + iio_bifur_table[3].ConfigIOU[2] = IIO_BIFURCATE_x4x4x4x4; + iio_bifur_table[3].ConfigIOU[3] = IIO_BIFURCATE_x4x4x4x4; + iio_bifur_table[3].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4; + + mupd->FspmConfig.DeEmphasisPtr = (UINT32) deemphasis_list; + mupd->FspmConfig.DeEmphasisNumber = CONFIG_MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET; + UINT8 *DeEmphasisConfig = (UINT8*) deemphasis_list; + + for (port = 0; port < CONFIG_MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET; port++) + { + DeEmphasisConfig[port] = 0x1; + } +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + + mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; + + /* Set Rank Margin Tool to disable. */ + mupd->FspmConfig.EnableRMT = 0x0; + /* Set Attempt Fast Boot to enable. */ + /* Enable - Portions of memory reference code will be skipped */ + /* when possible to increase boot speed on warm boots.*/ + /* Disable - Disables this feature. */ + /* Auto - Sets it to the MRC default setting. */ + mupd->FspmConfig.AttemptFastBoot = 0x1; + /* Set Attempt Fast Cold Boot to enable. */ + /* Enable - Portions of memory reference code will be skipped */ + /* when possible to increase boot speed on cold boots. */ + /* Disable - Disables this feature. */ + /* Auto - Sets it to the MRC default setting. */ + mupd->FspmConfig.AttemptFastBootCold = 0x1; + + /* Set MRC Promote Warnings to disable. */ + /* Determines if MRC warnings are promoted to system level. */ + mupd->FspmConfig.promoteMrcWarnings = 0x0; + /* Set Promote Warnings to disable. */ + /* Determines if warnings are promoted to system level. */ + mupd->FspmConfig.promoteWarnings = 0x0; + + /* Set FSP debug message to Normal */ + mupd->FspmConfig.serialDebugMsgLvl = 0x0; + + /* Disable FSP memory train results*/ + mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; + + /* Force 256MiB MMCONF (Segment0) only */ + mupd->FspmConfig.mmCfgSize = 0x2; + mupd->FspmConfig.PcieHotPlugEnable = 1; + + /* + * Disable unused IIO stack: + * Socket 0 : IIO1, IIO4 + * Socket 1 : IIO1, IIO2 + * Socket 2 : IIO1, IIO5 + * Socket 3 : IIO1, IIO5 + * Stack Disable bit mapping is: + * IIO stack number: 1 2 3 4 5 + * Stack Disable Bit: 1 5 3 2 4 + */ + UINT32 *sktbmp = (UINT32 *)&mupd->FspmConfig.StackDisableBitMap[0]; + sktbmp[0] = BIT(1) | BIT(2); + sktbmp[1] = BIT(1) | BIT(5); + sktbmp[2] = BIT(1) | BIT(4); + sktbmp[3] = BIT(1) | BIT(4); + mainboard_config_iio(mupd); + + + +}
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Patrick Rudolph (Code Review)