Bruce Griffith (Bruce.Griffith@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7246
-gerrit
commit 8dca6d52eed58606b6c8c3c79cf3517d9dccb341 Author: Bruce Griffith Bruce.Griffith@se-eng.com Date: Wed Oct 29 02:20:07 2014 -0600
AMD Bolton: Add some new PCI identifiers
Change-Id: Iada3d3e1dae5b69d2721b7cd309533eb121d74ef Signed-off-by: Bruce Griffith Bruce.Griffith@se-eng.com --- src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h | 18 ++++-------------- src/southbridge/amd/agesa/hudson/pci_devs.h | 7 ++++++- 2 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index f665471..05a7275 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -25,13 +25,7 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define FCH_INT_TABLE_SIZE 0x54 -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) -#define FCH_INT_TABLE_SIZE 0x42 -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON) -#define FCH_INT_TABLE_SIZE 0x63 -#endif +#define FCH_INT_TABLE_SIZE 128
#define PIRQ_NC 0x1F /* Not Used */ #define PIRQ_A 0x00 /* INT A */ @@ -47,9 +41,9 @@ #define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ #define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ #define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */ #define PIRQ_SCI 0x10 /* SCI IRQ */ #define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ #define PIRQ_ASF 0x12 /* ASF */ @@ -57,9 +51,7 @@ #define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define PIRQ_SD 0x17 /* SD */ -#endif #define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */ #define PIRQ_IMC2 0x22 /* IMC INT2 */ @@ -76,11 +68,9 @@ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON) -#define PIRQ_SD 0x17 /* SD */ #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ #endif #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define PIRQ_SD 0x42 /* SD 14h.7 */ #define PIRQ_GPP0 0x50 /* GPP INT 0 */ #define PIRQ_GPP1 0x51 /* GPP INT 1 */ #define PIRQ_GPP2 0x52 /* GPP INT 2 */ diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index b66a232..dd6c58c 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -28,6 +28,11 @@ #define XHCI_DEVID 0x7814 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
+#define XHCI2_DEV 0x10 +#define XHCI2_FUNC 1 +#define XHCI2_DEVID 0x7814 +#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) + /* SATA */ #define SATA_DEV 0x11 #define SATA_FUNC 0 @@ -56,7 +61,7 @@ #define EHCI1_FUNC 2 #define EHCI2_DEV 0x13 #define EHCI2_FUNC 2 -#define EHCI3_DEV 0x22 +#define EHCI3_DEV 0x16 #define EHCI3_FUNC 2 #define EHCI_DEVID 0x7808 #define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC)
-
Bruce Griffith