Change in coreboot[master]: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges()
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges()
The TPM memory MMIO range is always decoded by the PCH, regardless if it's LPC, SPI or fTPM.
Add the memory range to fixed MMIO ranges list to prevent LGMR register being written with this address. Reserved 8 KiB as that seems to be the minimal common reserved size for the TPM MMIO area.
Change-Id: I8f2257b55a712b936763cfd289c2c4b1633e8049 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/alderlake/espi.c M src/soc/intel/apollolake/lpc.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/lpc.c 9 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48658/1
diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c index c909030..f3c445a 100644 --- a/src/soc/intel/alderlake/espi.c +++ b/src/soc/intel/alderlake/espi.c @@ -27,6 +27,8 @@ */ static const struct lpc_mmio_range lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index ad9211b9..91b4b6e 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -9,7 +9,8 @@ #include "chip.h"
static const struct lpc_mmio_range apl_lpc_fixed_mmio_ranges[] = { - { 0xfed40000, 0x8000 }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0xfedc0000, 0x4000 }, { 0xfed20800, 16 }, { 0xfed20880, 8 }, diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index b21c117..b72c298 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -25,6 +25,8 @@ */ static const struct lpc_mmio_range cnl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index a531fcc..1ecd929 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -23,6 +23,8 @@ */ static const struct lpc_mmio_range ehl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 7f9ff2f..e4977be 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -24,6 +24,8 @@ */ static const struct lpc_mmio_range icl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index 0977857..3370999 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -24,6 +24,8 @@ */ static const struct lpc_mmio_range jsl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index f9c6639..7c80cbf 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -21,6 +21,8 @@
static const struct lpc_mmio_range skl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index acd3b12..d4ea81a 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -30,6 +30,8 @@ */ static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 3169545..370a020 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -10,6 +10,8 @@ #include <chip.h>
static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48658/1/src/soc/intel/apollolake/lp... File src/soc/intel/apollolake/lpc.c:
https://review.coreboot.org/c/coreboot/+/48658/1/src/soc/intel/apollolake/lp... PS1, Line 13: { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, APL only decodes locality 0, so this range could be shorter. It probably doesn't matter
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48658/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48658/1//COMMIT_MSG@13 PS1, Line 13: 8 KiB Not 0x5000? That's the value used by the TPM drivers for the ACPI region.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48658/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48658/1//COMMIT_MSG@13 PS1, Line 13: 8 KiB
Not 0x5000? That's the value used by the TPM drivers for the ACPI region.
Oh right, it's 0x8000 or 0x10000. I'll update the commit message
Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48658
to look at the new patch set (#2).
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges()
The TPM memory MMIO range is always decoded by the PCH, regardless if it's LPC, SPI or fTPM.
Add the memory range to fixed MMIO ranges list to prevent LGMR register being written with this address. Reserved 32 KiB as that seems to be the minimal common reserved size for the TPM MMIO area.
Change-Id: I8f2257b55a712b936763cfd289c2c4b1633e8049 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/alderlake/espi.c M src/soc/intel/apollolake/lpc.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/lpc.c 9 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48658/2
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48658/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48658/1//COMMIT_MSG@13 PS1, Line 13: 8 KiB
Oh right, it's 0x8000 or 0x10000. […]
Done
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48658/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48658/1//COMMIT_MSG@13 PS1, Line 13: 8 KiB
Done
Where do you see those values? In the TCG PTP and TIS specifications, I see 0x5000 defined, 0x1000 for each locality. The PTP specification reserves an additional 0x1000 as "non-locality specific registers."
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48658/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48658/1//COMMIT_MSG@13 PS1, Line 13: 8 KiB
Where do you see those values? In the TCG PTP and TIS specifications, I see 0x5000 defined, 0x1000 f […]
It's in every Intel® * Series Chipset Family Platform Controller Hub Vol 1 datasheet.
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48658/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48658/1//COMMIT_MSG@13 PS1, Line 13: 8 KiB
It's in every Intel® * Series Chipset Family Platform Controller Hub Vol 1 datasheet.
Ack. Thanks.
Attention is currently required from: Patrick Rudolph, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 2: Code-Review+1
Attention is currently required from: Nico Huber, Patrick Rudolph, Tim Wawrzynczak, Subrata Banik. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/lpc.c:
https://review.coreboot.org/c/coreboot/+/48658/comment/33ee61b3_01afaf22 PS2, Line 13: { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, : { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, : AFAIUI these Kconfigs are only there for overriding the fixed address in case the tpm doesn't comply with the TCG spec.
If a user/board overrides this value, we should not add that variable value to the lpc fixed ranges. Also, the Kconfig doesn't change the hardware (iow when the Kconfig changes, the soc will still decode 0xfed4000 and it should still be here).
IMO we should define the ranges/sizes per soc in include/soc/iomap.h and use these fixed ones here.
Attention is currently required from: Nico Huber, Patrick Rudolph, Subrata Banik. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/tigerlake/espi.c:
https://review.coreboot.org/c/coreboot/+/48658/comment/a3027019_bdb7fb74 PS2, Line 33: 0x8000 64K for TGL
Attention is currently required from: Nico Huber, Patrick Rudolph, Tim Wawrzynczak, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/tigerlake/espi.c:
https://review.coreboot.org/c/coreboot/+/48658/comment/09504f74_daad61cf PS2, Line 33: 0x8000
64K for TGL
Which document (title and/or doc number) did you find this information in? It would be good to mention this document in the comment above.
Attention is currently required from: Nico Huber, Patrick Rudolph, Tim Wawrzynczak, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/espi.c:
https://review.coreboot.org/c/coreboot/+/48658/comment/c6cc82c3_127359c1 PS2, Line 30: 0x8000 Knowing that TGL uses 64 KiB, maybe ADL uses 64 KiB as well. Subrata, could you please confirm?
Attention is currently required from: Nico Huber, Patrick Rudolph, Tim Wawrzynczak, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/apollolake/lpc.c:
https://review.coreboot.org/c/coreboot/+/48658/comment/286ff18f_e862c8ad PS2, Line 12: 0x8000 Maybe write these values as `32 * KiB`?
Attention is currently required from: Nico Huber, Patrick Rudolph, Tim Wawrzynczak, Subrata Banik. Hello build bot (Jenkins), Nico Huber, Benjamin Doron, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48658
to look at the new patch set (#3).
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges()
The TPM memory MMIO range is always decoded by the PCH, regardless if it's LPC, SPI or fTPM.
Add the memory range to fixed MMIO ranges list to prevent LGMR register being written with this address.
This approach doesn't use CONFIG_TPM_TIS_BASE_ADDRESS as the decoded memory area doesn't change with CONFIG_TPM_TIS_BASE_ADDRESS being modified.
Change-Id: I8f2257b55a712b936763cfd289c2c4b1633e8049 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/alderlake/espi.c M src/soc/intel/alderlake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/lpc.c M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/cannonlake/lpc.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/elkhartlake/include/soc/iomap.h M src/soc/intel/icelake/espi.c M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/jasperlake/espi.c M src/soc/intel/jasperlake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/lpc.c 18 files changed, 39 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48658/3
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 3:
(2 comments)
File src/soc/intel/tigerlake/espi.c:
https://review.coreboot.org/c/coreboot/+/48658/comment/c79706ab_0e6b20a6 PS2, Line 33: 0x8000
Which document (title and/or doc number) did you find this information in? It would be good to menti […]
Done
File src/soc/intel/xeon_sp/lpc.c:
https://review.coreboot.org/c/coreboot/+/48658/comment/e6195ae7_f4e32f07 PS2, Line 13: { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, : { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, :
AFAIUI these Kconfigs are only there for overriding the fixed address in case the tpm doesn't comply […]
Done
Attention is currently required from: Nico Huber, Patrick Rudolph, Tim Wawrzynczak, Angel Pons, Subrata Banik. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 3:
(5 comments)
File src/soc/intel/alderlake/espi.c:
https://review.coreboot.org/c/coreboot/+/48658/comment/154c1799_f07af6c7 PS3, Line 30: { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, : { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, : TPM_BASE_*
File src/soc/intel/apollolake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/48658/comment/547b1f02_90cf2328 PS3, Line 40: /* No TXT support. Only Locality 0 is forwared to TPM */ : #define TPM_BASE_ADDRESS 0xfed40000 : #define TPM_BASE_SIZE 0x1000 : checked with intel doc# 334818
File src/soc/intel/cannonlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/48658/comment/38f3fbf8_335384a8 PS3, Line 24: #define TPM_BASE_ADDRESS 0xfed40000 : #define TPM_BASE_SIZE 0x8000 : checked with intel doc# 620854-002, 337867-003
File src/soc/intel/skylake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/48658/comment/95a004d3_24979965 PS3, Line 27: #define TPM_BASE_SIZE 0x8000 checked with intel doc# 332995-003EN, 332690-006EN
File src/soc/intel/xeon_sp/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/48658/comment/9097466c_bec5bc2d PS3, Line 35: #define TPM_BASE_ADDRESS 0xfed40000 : #define TPM_BASE_SIZE 0x8000 : checked with intel doc# 547817, rev1.5
Attention is currently required from: Nico Huber, Patrick Rudolph, Tim Wawrzynczak, Angel Pons, Subrata Banik. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 3: Code-Review+1
Attention is currently required from: Nico Huber, Patrick Rudolph, Tim Wawrzynczak, Angel Pons, Subrata Banik. Hello build bot (Jenkins), Nico Huber, Benjamin Doron, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48658
to look at the new patch set (#4).
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges()
The TPM memory MMIO range is always decoded by the PCH, regardless if it's LPC, SPI or fTPM.
Add the memory range to fixed MMIO ranges list to prevent LGMR register being written with this address.
This approach doesn't use CONFIG_TPM_TIS_BASE_ADDRESS as the decoded memory area doesn't change with CONFIG_TPM_TIS_BASE_ADDRESS being modified.
Change-Id: I8f2257b55a712b936763cfd289c2c4b1633e8049 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/alderlake/espi.c M src/soc/intel/alderlake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/lpc.c M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/cannonlake/lpc.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/elkhartlake/include/soc/iomap.h M src/soc/intel/icelake/espi.c M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/jasperlake/espi.c M src/soc/intel/jasperlake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/lpc.c 18 files changed, 38 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48658/4
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/alderlake/espi.c:
https://review.coreboot.org/c/coreboot/+/48658/comment/f09a5771_8a631f90 PS3, Line 30: { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, : { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, :
TPM_BASE_*
Done
Attention is currently required from: Nico Huber, Patrick Rudolph, Angel Pons, Subrata Banik, Michael Niewöhner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 4:
(2 comments)
File src/soc/intel/alderlake/espi.c:
https://review.coreboot.org/c/coreboot/+/48658/comment/86177e7a_1c4f0ebe PS2, Line 30: 0x8000
Knowing that TGL uses 64 KiB, maybe ADL uses 64 KiB as well. […]
ADL shows 64 KiB here in the #627270 bios core/uncore spec, but #626817 PCH EDS vol 1 shows 32 KiB here... Subrata, could you help confirm the correct value?
File src/soc/intel/tigerlake/espi.c:
https://review.coreboot.org/c/coreboot/+/48658/comment/7db62047_5be02485 PS2, Line 33: 0x8000
Done
Ok, another mismatch like ADL, BIOS core/uncore spec (#611569) shows 64 KiB but PCH EDS vol. 1 (#576591) shows 32 KiB. Subrata, could you help here?
Attention is currently required from: Patrick Rudolph, Angel Pons, Subrata Banik, Michael Niewöhner. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4: I was invited late, so no idea if this was debated yet: I don't think the code around soc_get_fixed_mmio_ranges() is worth saving. The idea to use PCH_PRESERVED_BASE_* there seems completely wrong and any comprehensive list (like tried on APL) would kind of compete with resource lists in our devicetree.
So far, we couldn't see any device that needs the (most likely untested) mechanism around LGMR in soc/intel/. If nobody finds one, I would prefer to just drop the code.
Attention is currently required from: Nico Huber, Patrick Rudolph, Angel Pons, Subrata Banik. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
So far, we couldn't see any device that needs the (most likely untested) mechanism around LGMR in soc/intel/. If nobody finds one, I would prefer to just drop the code.
Not yet. As soon as I get lgmr working on the L141CU, it's EC will be the first one to use it. I want to have a look at the allocation stuff we discussed on IRC, then.
However, that doesn't prevent us from dropping the currently unused code and introduce a proper rewrite, as soon as we need it
Attention is currently required from: Nico Huber, Patrick Rudolph, Angel Pons, Subrata Banik. Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4: Any updates to this patch?
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/48658?usp=email )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Benjamin Doron (Code Review)
-
Michael Niewöhner (Code Review)
-
Nico Huber (Code Review)
-
Patrick Rudolph (Code Review)
-
Rocky Phagura (Code Review)
-
Stefan Reinauer (Code Review)
-
Tim Wawrzynczak (Code Review)