Hello Raul Rangel, Marshall Dawson, Marshall Dawson, Eric Peers,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39999
to review the following change.
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
soc/amd/common/psp: Consolidate FW blob load functions
The commands used in Family 15h for loading the SMU FW blobs out of flash had already been defined differently in Family 17h. To begin removing Family 15h dependencies from the common/psp, change the definitions of blob type to no longer match the Family 15h commands.
Consolidate the two functions used for interpreting the command and applying the command into a single one.
TEST: Verify PSP functionality on google/grunt
Change-Id: Ic5a4926175d50c01b70ff9b10908c38b3cbe8f35 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Reviewed-on: https://chromium-review.googlesource.com/2020364 Reviewed-by: Eric Peers epeers@google.com Reviewed-by: Raul E Rangel rrangel@chromium.org Tested-by: Eric Peers epeers@google.com --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c 4 files changed, 40 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39999/1
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index b730293..494f174 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -115,6 +115,11 @@ * MBOX_BIOS_CMD_SMU_FW2 to load SMU FW2 blob. * name: cbfs file name */ -int psp_load_named_blob(int type, const char *name); +enum psp_blob_type { + BLOB_SMU_FW, + BLOB_SMU_FW2, +}; + +int psp_load_named_blob(enum psp_blob_type type, const char *name);
#endif /* __AMD_PSP_H__ */ diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 0294422..a32c9b7 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -288,53 +288,52 @@ /* * Tell the PSP to load a firmware blob from a location in the BIOS image. */ -static int psp_load_blob(int type, void *addr) +int psp_load_named_blob(enum psp_blob_type type, const char *name) { int cmd_status; - - if (!CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) { - printk(BIOS_ERR, "BUG: Selectable firmware is not supported\n"); - return PSPSTS_UNSUPPORTED; - } - - /* only two types currently supported */ - if (type != MBOX_BIOS_CMD_SMU_FW && type != MBOX_BIOS_CMD_SMU_FW2) { - printk(BIOS_ERR, "BUG: Invalid PSP blob type %x\n", type); - return PSPSTS_INVALID_BLOB; - } - - printk(BIOS_DEBUG, "PSP: Load blob type %x from @%p... ", type, addr); - - /* Blob commands use the buffer registers as data, not pointer to buf */ - cmd_status = send_psp_command(type, addr); - - print_cmd_status(cmd_status, NULL); - - return cmd_status; -} - -int psp_load_named_blob(int type, const char *name) -{ + u32 command; void *blob; struct cbfsf cbfs_file; struct region_device rdev; - int r; + + switch (type) { + case BLOB_SMU_FW: + command = MBOX_BIOS_CMD_SMU_FW; + break; + case BLOB_SMU_FW2: + command = MBOX_BIOS_CMD_SMU_FW2; + break; + default: + printk(BIOS_ERR, "BUG: Invalid PSP blob type %x\n", type); + return -PSPSTS_INVALID_BLOB; + } + + if (!CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW) && + (type == BLOB_SMU_FW || type == BLOB_SMU_FW2)) { + printk(BIOS_ERR, "BUG: Selectable firmware is not supported\n"); + return -PSPSTS_UNSUPPORTED; + }
if (cbfs_boot_locate(&cbfs_file, name, NULL)) { printk(BIOS_ERR, "BUG: Cannot locate blob for PSP loading\n"); - return PSPSTS_INVALID_NAME; + return -PSPSTS_INVALID_NAME; }
cbfs_file_data(&rdev, &cbfs_file); blob = rdev_mmap_full(&rdev); - if (blob) { - r = psp_load_blob(type, blob); - rdev_munmap(&rdev, blob); - } else { + if (!blob) { printk(BIOS_ERR, "BUG: Cannot map blob for PSP loading\n"); - return PSPSTS_INVALID_NAME; + return -PSPSTS_INVALID_NAME; } - return r; + + printk(BIOS_DEBUG, "PSP: Load blob type %x from @%p... ", type, blob); + + /* Blob commands use the buffer registers as data, not pointer to buf */ + cmd_status = send_psp_command(command, blob); + print_cmd_status(cmd_status, NULL); + + rdev_munmap(&rdev, blob); + return cmd_status; }
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index aa3c322..f08c12f 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -160,7 +160,7 @@ if (!s3_resume) { post_code(0x46); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); + psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2");
post_code(0x47); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 0a209b0..efe75b7 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -61,7 +61,7 @@ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
- psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); + psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); }
static void agesa_call(void)
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39999 )
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
Patch Set 1: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39999 )
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... File src/soc/amd/common/block/psp/psp.c:
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... PS1, Line 312: (type == BLOB_SMU_FW || type == BLOB_SMU_FW2) This is asserted by the switch statement above already, so it is redundant.
Furthermore, dropping this check would result in a statically-evaluated condition. Maybe this could be checked statically instead, but that doesn't need to happen in this change.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39999 )
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... File src/soc/amd/common/block/psp/psp.c:
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... PS1, Line 312: (type == BLOB_SMU_FW || type == BLOB_SMU_FW2)
This is asserted by the switch statement above already, so it is redundant. […]
good point. will do that in a follow-up, since this in in the middle of short patch train that is already verified on stoneyridge hardware, which i don't have at the moment. will mark this as resolved when i've uploaded said patch
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39999 )
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... File src/soc/amd/common/block/psp/psp.c:
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... PS1, Line 312: (type == BLOB_SMU_FW || type == BLOB_SMU_FW2)
good point. […]
hm, maybe i do fix this here, since this is newly introduced in this patch, so that change should belong in here. i'll see
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39999 )
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... File src/soc/amd/common/block/psp/psp.c:
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... PS1, Line 312: (type == BLOB_SMU_FW || type == BLOB_SMU_FW2)
hm, maybe i do fix this here, since this is newly introduced in this patch, so that change should be […]
It's been a while since I've considered this, however I'd likely done it intentionally to cover the possibility that there could be future loadable blob types. However I agree it's redundant as the source sits. The switch above would be used to weed out all non-understood blobs. For SMU_FW & FW2, there's the additional requirement that the feature must be built into the BIOS.
In reality, I don't currently foresee any new loadable blobs in the future. So I'd be OK with removing the redundancy and adding a comment instead.
Hello build bot (Jenkins), Raul Rangel, Marshall Dawson, Marshall Dawson, Angel Pons, Eric Peers,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39999
to look at the new patch set (#2).
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
soc/amd/common/psp: Consolidate FW blob load functions
The commands used in Family 15h for loading the SMU FW blobs out of flash had already been defined differently in Family 17h. To begin removing Family 15h dependencies from the common/psp, change the definitions of blob type to no longer match the Family 15h commands.
Consolidate the two functions used for interpreting the command and applying the command into a single one.
TEST: Verify PSP functionality on google/grunt
Change-Id: Ic5a4926175d50c01b70ff9b10908c38b3cbe8f35 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Reviewed-on: https://chromium-review.googlesource.com/2020364 Reviewed-by: Eric Peers epeers@google.com Reviewed-by: Raul E Rangel rrangel@chromium.org Tested-by: Eric Peers epeers@google.com Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c 4 files changed, 39 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39999/2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39999 )
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... File src/soc/amd/common/block/psp/psp.c:
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... PS1, Line 312: (type == BLOB_SMU_FW || type == BLOB_SMU_FW2)
It's been a while since I've considered this, however I'd likely done it intentionally to cover the […]
i removed this now; should i add a comment about the removed additional checks that are currently always true?
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39999 )
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... File src/soc/amd/common/block/psp/psp.c:
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... PS1, Line 312: (type == BLOB_SMU_FW || type == BLOB_SMU_FW2)
i removed this now; should i add a comment about the removed additional checks that are currently al […]
Yes, I would add something. Maybe simply a comment above line 311 that states something like "The only two currently supported types require selectable SMU firmware". That should be sufficient to catch someone's eye later and suggest the check needs to be reworked. I'm OK with more detail too.
Hello build bot (Jenkins), Raul Rangel, Marshall Dawson, Marshall Dawson, Angel Pons, Eric Peers,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39999
to look at the new patch set (#3).
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
soc/amd/common/psp: Consolidate FW blob load functions
The commands used in Family 15h for loading the SMU FW blobs out of flash had already been defined differently in Family 17h. To begin removing Family 15h dependencies from the common/psp, change the definitions of blob type to no longer match the Family 15h commands.
Consolidate the two functions used for interpreting the command and applying the command into a single one.
TEST: Verify PSP functionality on google/grunt
Change-Id: Ic5a4926175d50c01b70ff9b10908c38b3cbe8f35 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Reviewed-on: https://chromium-review.googlesource.com/2020364 Reviewed-by: Eric Peers epeers@google.com Reviewed-by: Raul E Rangel rrangel@chromium.org Tested-by: Eric Peers epeers@google.com Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c 4 files changed, 40 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39999/3
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39999 )
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... File src/soc/amd/common/block/psp/psp.c:
https://review.coreboot.org/c/coreboot/+/39999/1/src/soc/amd/common/block/ps... PS1, Line 312: (type == BLOB_SMU_FW || type == BLOB_SMU_FW2)
Yes, I would add something. […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39999 )
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
Patch Set 3: Code-Review+2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39999 )
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
Patch Set 3: Code-Review+2
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39999 )
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
Patch Set 3: Code-Review+1
Hello build bot (Jenkins), Raul Rangel, Marshall Dawson, Marshall Dawson, Angel Pons, Eric Peers,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39999
to look at the new patch set (#4).
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
soc/amd/common/psp: Consolidate FW blob load functions
The commands used in Family 15h for loading the SMU FW blobs out of flash had already been defined differently in Family 17h. To begin removing Family 15h dependencies from the common/psp, change the definitions of blob type to no longer match the Family 15h commands.
Consolidate the two functions used for interpreting the command and applying the command into a single one.
BUG=b:130660285 TEST: Verify PSP functionality on google/grunt
Change-Id: Ic5a4926175d50c01b70ff9b10908c38b3cbe8f35 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Reviewed-on: https://chromium-review.googlesource.com/2020364 Reviewed-by: Eric Peers epeers@google.com Reviewed-by: Raul E Rangel rrangel@chromium.org Tested-by: Eric Peers epeers@google.com Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c 4 files changed, 40 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39999/4
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39999 )
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
soc/amd/common/psp: Consolidate FW blob load functions
The commands used in Family 15h for loading the SMU FW blobs out of flash had already been defined differently in Family 17h. To begin removing Family 15h dependencies from the common/psp, change the definitions of blob type to no longer match the Family 15h commands.
Consolidate the two functions used for interpreting the command and applying the command into a single one.
BUG=b:130660285 TEST: Verify PSP functionality on google/grunt
Change-Id: Ic5a4926175d50c01b70ff9b10908c38b3cbe8f35 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Reviewed-on: https://chromium-review.googlesource.com/2020364 Reviewed-by: Eric Peers epeers@google.com Reviewed-by: Raul E Rangel rrangel@chromium.org Tested-by: Eric Peers epeers@google.com Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/39999 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c 4 files changed, 40 insertions(+), 36 deletions(-)
Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index b730293..494f174 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -115,6 +115,11 @@ * MBOX_BIOS_CMD_SMU_FW2 to load SMU FW2 blob. * name: cbfs file name */ -int psp_load_named_blob(int type, const char *name); +enum psp_blob_type { + BLOB_SMU_FW, + BLOB_SMU_FW2, +}; + +int psp_load_named_blob(enum psp_blob_type type, const char *name);
#endif /* __AMD_PSP_H__ */ diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 0294422..9c053c2 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -288,53 +288,52 @@ /* * Tell the PSP to load a firmware blob from a location in the BIOS image. */ -static int psp_load_blob(int type, void *addr) +int psp_load_named_blob(enum psp_blob_type type, const char *name) { int cmd_status; - - if (!CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) { - printk(BIOS_ERR, "BUG: Selectable firmware is not supported\n"); - return PSPSTS_UNSUPPORTED; - } - - /* only two types currently supported */ - if (type != MBOX_BIOS_CMD_SMU_FW && type != MBOX_BIOS_CMD_SMU_FW2) { - printk(BIOS_ERR, "BUG: Invalid PSP blob type %x\n", type); - return PSPSTS_INVALID_BLOB; - } - - printk(BIOS_DEBUG, "PSP: Load blob type %x from @%p... ", type, addr); - - /* Blob commands use the buffer registers as data, not pointer to buf */ - cmd_status = send_psp_command(type, addr); - - print_cmd_status(cmd_status, NULL); - - return cmd_status; -} - -int psp_load_named_blob(int type, const char *name) -{ + u32 command; void *blob; struct cbfsf cbfs_file; struct region_device rdev; - int r; + + switch (type) { + case BLOB_SMU_FW: + command = MBOX_BIOS_CMD_SMU_FW; + break; + case BLOB_SMU_FW2: + command = MBOX_BIOS_CMD_SMU_FW2; + break; + default: + printk(BIOS_ERR, "BUG: Invalid PSP blob type %x\n", type); + return -PSPSTS_INVALID_BLOB; + } + + /* type can only be BLOB_SMU_FW or BLOB_SMU_FW2 here, so don't re-check for this */ + if (!CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) { + printk(BIOS_ERR, "BUG: Selectable firmware is not supported\n"); + return -PSPSTS_UNSUPPORTED; + }
if (cbfs_boot_locate(&cbfs_file, name, NULL)) { printk(BIOS_ERR, "BUG: Cannot locate blob for PSP loading\n"); - return PSPSTS_INVALID_NAME; + return -PSPSTS_INVALID_NAME; }
cbfs_file_data(&rdev, &cbfs_file); blob = rdev_mmap_full(&rdev); - if (blob) { - r = psp_load_blob(type, blob); - rdev_munmap(&rdev, blob); - } else { + if (!blob) { printk(BIOS_ERR, "BUG: Cannot map blob for PSP loading\n"); - return PSPSTS_INVALID_NAME; + return -PSPSTS_INVALID_NAME; } - return r; + + printk(BIOS_DEBUG, "PSP: Load blob type %x from @%p... ", type, blob); + + /* Blob commands use the buffer registers as data, not pointer to buf */ + cmd_status = send_psp_command(command, blob); + print_cmd_status(cmd_status, NULL); + + rdev_munmap(&rdev, blob); + return cmd_status; }
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index aa3c322..f08c12f 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -160,7 +160,7 @@ if (!s3_resume) { post_code(0x46); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); + psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2");
post_code(0x47); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 0a209b0..efe75b7 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -61,7 +61,7 @@ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
- psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); + psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); }
static void agesa_call(void)
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39999 )
Change subject: soc/amd/common/psp: Consolidate FW blob load functions ......................................................................
Patch Set 5:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1998 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1997 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1996
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Angel Pons (Code Review)
-
Felix Held (Code Review)
-
Marshall Dawson (Code Review)
-
Raul Rangel (Code Review)