Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47041 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425
Update FSP headers for Tiger Lake platform generated based on FSP version 3425. Previous version was 3373.
BUG=b:172045149 BRANCH=none TEST=build and boot delbin
Change-Id: I58d165d452c8c6ae2eec92524109a568f7e581a9 --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/47041/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 28592cd..6038b13 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2498,7 +2498,7 @@
/** Offset 0x091C - Reserved **/ - UINT8 Reserved45[12]; + UINT8 Reserved45[36]; } FSP_M_CONFIG;
/** Fsp M UPD Configuration @@ -2517,11 +2517,11 @@ **/ FSP_M_CONFIG FspmConfig;
-/** Offset 0x0928 +/** Offset 0x0940 **/ UINT8 UnusedUpdSpace27[6];
-/** Offset 0x092E +/** Offset 0x0946 **/ UINT16 UpdTerminator; } FSPM_UPD;
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47041
to look at the new patch set (#2).
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425
Update FSP headers for Tiger Lake platform generated based on FSP version 3425. Previous version was 3373.
BUG=b:172045149 BRANCH=none TEST=build and boot delbin
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I58d165d452c8c6ae2eec92524109a568f7e581a9 --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/47041/2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47041 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425 ......................................................................
Patch Set 2: Code-Review+1
Dossym Nurmukhanov has uploaded a new patch set (#3) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/47041 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425
Update FSP headers for Tiger Lake platform generated based on FSP version 3425. Previous version was 3373.
BUG=b:172045149 BRANCH=none TEST=build and boot delbin
Cq-Depend:chrome-internal:3373431 Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I58d165d452c8c6ae2eec92524109a568f7e581a9 --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/47041/3
Dossym Nurmukhanov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47041 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425 ......................................................................
Patch Set 3: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47041 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425 ......................................................................
Patch Set 3: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47041 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425
Update FSP headers for Tiger Lake platform generated based on FSP version 3425. Previous version was 3373.
BUG=b:172045149 BRANCH=none TEST=build and boot delbin
Cq-Depend:chrome-internal:3373431 Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I58d165d452c8c6ae2eec92524109a568f7e581a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47041 Reviewed-by: Dossym Nurmukhanov dossym@google.com Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, but someone else must approve Dossym Nurmukhanov: Looks good to me, approved
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 28592cd..6038b13 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2498,7 +2498,7 @@
/** Offset 0x091C - Reserved **/ - UINT8 Reserved45[12]; + UINT8 Reserved45[36]; } FSP_M_CONFIG;
/** Fsp M UPD Configuration @@ -2517,11 +2517,11 @@ **/ FSP_M_CONFIG FspmConfig;
-/** Offset 0x0928 +/** Offset 0x0940 **/ UINT8 UnusedUpdSpace27[6];
-/** Offset 0x092E +/** Offset 0x0946 **/ UINT16 UpdTerminator; } FSPM_UPD;