the following patch was just integrated into master: commit d6463dd42c0b5688601ce6de5e7cff16926df297 Author: Shaunak Saha shaunak.saha@intel.com Date: Wed May 25 11:34:43 2016 -0700
intel/apollolake: Add support to enable google ChromeEC
ChromeEC is needed for EC controlled features to work properly. This patch adds neccessary support in soc/intel so that mainboard asl files can include the ChromeEC e.g. PNOT method and LPCB and also the nvs fields.
BUG = 53096 TEST = This patch is needed by the mainboard specific ASL change to include src/ec/google/chromeec/acpi/ec.asl
Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9 Signed-off-by: Shaunak Saha shaunak.saha@intel.com Reviewed-on: https://review.coreboot.org/14967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin adurbin@chromium.org
See https://review.coreboot.org/14967 for details.
-gerrit