Attention is currently required from: Wonkyu Kim, Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61283 )
Change subject: soc/intel/common: Expand the Primary to Sideband bridge ......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Based on the "dev" to refer to different P2SB BAR while referring to mmio_resource?
1. As mentioned, there are common features across p2sb and p2sb2 like the P2SB generic configuration registers offset, etc. But there also exist difference, i.e lock(mask EPs and hide) function in which the masking EPs only appears valid and executed towards p2sb(you might probe the fsp code execution). p2sb and p2sb2 have different addressing regions(32 bit vs 64 bit) and size. It seems proper and clear to have a p2sb_lib.c which has the real common code like hide/unhide/enable_bar. p2sb and p2sb2 hold their own framework and dedicated functions (like hpet/apic for p2sb.c, etc) as treated different pci devices. 2. Can you consider to change the term "SOC" usage in CB:61297? p2sb is referred to PCH besides the CPU die. MTL has the additional IOE die with p2sb2. As you might recall, future platforms besides the MTL drop the IOE with different architecture, like computerX die, ChipsetX and PCH into SoC die, etc. It seems aligned to replace the "SOC" with "PCH". We will expand and have PCH/IOE for MTL and PCH/ChipsetX for future platforms.
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John Zhao (Code Review)