Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52201 )
Change subject: mb/intel/adlrvp_m: Add UART0 GPIO config for ADL-M RVP ......................................................................
mb/intel/adlrvp_m: Add UART0 GPIO config for ADL-M RVP
This patch adds UART0 config in early GPIO table
Branch=None Test=Build coreboot and boot on ADLRVP-M board. Check UART logs
Signed-off-by: Anil Kumar anil.kumar.k@intel.com Change-Id: Ic0cc955a02936b74f44fed55a9f4b8054646681a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52201 Reviewed-by: Bora Guvendik bora.guvendik@intel.com Reviewed-by: Bernardo Perez Priego bernardo.perez.priego@intel.com Reviewed-by: Varshit B Pandya varshit.b.pandya@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/adlrvp/early_gpio_m.c 1 file changed, 10 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Varshit B Pandya: Looks good to me, but someone else must approve Bernardo Perez Priego: Looks good to me, but someone else must approve Anil Kumar K: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c index c257004..116d3c6 100644 --- a/src/mainboard/intel/adlrvp/early_gpio_m.c +++ b/src/mainboard/intel/adlrvp/early_gpio_m.c @@ -13,7 +13,17 @@ PAD_CFG_GPO(GPP_A8, 1, DEEP), };
+static const struct pad_config early_uart_gpio_table[] = { + /* UART0 RX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* UART0 TX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + void variant_configure_early_gpio_pads(void) { + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); }