Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39385 )
Change subject: mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree ......................................................................
mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are set up in romstage, so it makes no sense to rewrite their values in ramstage.
Tested, my Asus P5QPL-AM still boots.
Change-Id: Ic47f96d12420ebcc70ab5cea940c4c09620c03ca Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb 1 file changed, 6 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/39385/1
diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb index e84fd8a..3f56fdf 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb +++ b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb @@ -22,9 +22,6 @@ chip superio/winbond/w83627dhg device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel port - # global - irq 0x2c = 0x92 - # parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 @@ -40,16 +37,12 @@ irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # SPI - device pnp 2e.7 on end # GPIO6 (all input) - device pnp 2e.8 off end # WDT0#, PLED - device pnp 2e.9 off end # GPIO2 - device pnp 2e.109 on # GPIO3 - irq 0xf0 = 0xf3 - end - device pnp 2e.209 on # GPIO4 - irq 0xf4 = 0x00 - end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 (all input) + device pnp 2e.8 off end # WDT0#, PLED + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on end # GPIO3 + device pnp 2e.209 on end # GPIO4 device pnp 2e.309 off end # GPIO5 device pnp 2e.a on # ACPI irq 0x70 = 0
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39385 )
Change subject: mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/39385/1/src/mainboard/asus/p5qpl-am... File src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39385/1/src/mainboard/asus/p5qpl-am... PS1, Line 45: maybe only one whitespace?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39385 )
Change subject: mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39385/1/src/mainboard/asus/p5qpl-am... File src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39385/1/src/mainboard/asus/p5qpl-am... PS1, Line 45:
maybe only one whitespace?
There's the `device pnp 2e.309 off end` underneath though, then it is not aligned
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Arthur Heymans, HAOUAS Elyes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39385
to look at the new patch set (#2).
Change subject: mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree ......................................................................
mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are set up in romstage, so it makes no sense to rewrite their values in ramstage.
Tested, my Asus P5QPL-AM still boots.
Change-Id: Ic47f96d12420ebcc70ab5cea940c4c09620c03ca Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb 1 file changed, 6 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/39385/2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39385 )
Change subject: mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39385 )
Change subject: mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39385/1/src/mainboard/asus/p5qpl-am... File src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39385/1/src/mainboard/asus/p5qpl-am... PS1, Line 45:
There's the `device pnp 2e. […]
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39385 )
Change subject: mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39385 )
Change subject: mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree ......................................................................
mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are set up in romstage, so it makes no sense to rewrite their values in ramstage.
Tested, my Asus P5QPL-AM still boots.
Change-Id: Ic47f96d12420ebcc70ab5cea940c4c09620c03ca Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39385 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Nico Huber nico.h@gmx.de --- M src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb 1 file changed, 6 insertions(+), 13 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb index e84fd8a..1305bff 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb +++ b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb @@ -22,9 +22,6 @@ chip superio/winbond/w83627dhg device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel port - # global - irq 0x2c = 0x92 - # parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 @@ -40,16 +37,12 @@ irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # SPI - device pnp 2e.7 on end # GPIO6 (all input) - device pnp 2e.8 off end # WDT0#, PLED - device pnp 2e.9 off end # GPIO2 - device pnp 2e.109 on # GPIO3 - irq 0xf0 = 0xf3 - end - device pnp 2e.209 on # GPIO4 - irq 0xf4 = 0x00 - end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 (all input) + device pnp 2e.8 off end # WDT0#, PLED + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on end # GPIO3 + device pnp 2e.209 on end # GPIO4 device pnp 2e.309 off end # GPIO5 device pnp 2e.a on # ACPI irq 0x70 = 0
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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HAOUAS Elyes (Code Review)
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Nico Huber (Code Review)
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Patrick Georgi (Code Review)