[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions

[Cliff Huang (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Subrata Banik.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )

Change subject: soc/intel/common/block/pmc: Add GPE1 functions
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Patch Set 7:

(9 comments)

File src/soc/intel/common/block/pmc/pmclib.c:

https://review.coreboot.org/c/coreboot/+/84104/comment/05ddc183_befa9a8d?usp... :
PS3, Line 406: pmc_clear_gpi_gpe0_status
> > gpi_gpe0 means the general GPI event in GPE0. GPE1 only contains Intel's std events. […]

Subrata,

pmc_disable_all_gpe() is called in smm_southbridge_enable function in  src/soc/intel/common/block/smm/smm.c.

from SOC cpu.c, we have MP OPS:

.pre_mp_smm_init = smm_initialize,    <- NOTE: GPE STS bits are cleared here

.post_mp_init = post_mp_init,         <- NOTE: GPE EN bits are cleared here

This should still be earlier enough.

File src/soc/intel/common/block/pmc/pmclib.c:

https://review.coreboot.org/c/coreboot/+/84104/comment/7fa9afc6_43c665c0?usp... :
PS7, Line 306: 0
> this should be NULL ? as you are returning `char *`

Done

https://review.coreboot.org/c/coreboot/+/84104/comment/096aedda_cd23f62a?usp... :
PS7, Line 341: pmc_clear_gpi_gpe0_status
> sure. working on this.

I do a search and only the existing gpe event disabling functions need to cover GPE1 EN bits if _HAVE_GPE1. By doing this, no _gpe_function needs to be renamed outside of pmclib.c.

In addition, I delete the GPE event enable functions since not used. CB should not enable these events during boot, anyways.

https://review.coreboot.org/c/coreboot/+/84104/comment/93761458_c330ea5c?usp... :
PS7, Line 379: gpe_sts
> check the NULL pointer at line 381

Done

https://review.coreboot.org/c/coreboot/+/84104/comment/73efea28_9331eb8f?usp... :
PS7, Line 381: 	int i;
> drop

Done

https://review.coreboot.org/c/coreboot/+/84104/comment/4c6fabb1_8d2596be?usp... :
PS7, Line 383: i
> ```int i```

Done

https://review.coreboot.org/c/coreboot/+/84104/comment/78107c0a_bf24424a?usp... :
PS7, Line 393: 	int i;
> same

Done

https://review.coreboot.org/c/coreboot/+/84104/comment/caaee312_6089af7c?usp... :
PS7, Line 396: sts_arr =
> missing NULL check ?

Done

https://review.coreboot.org/c/coreboot/+/84104/comment/18023c22_27025b52?usp... :
PS7, Line 406: 	if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) {
> WDYT […]

Done