[M] Change in coreboot[master]: sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70114 )
Change subject: sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary} ......................................................................
sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}
Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81 Signed-off-by: Elyes Haouas ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114 Reviewed-by: Eric Lai eric_lai@quanta.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/mainboard.c M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/mainboard/lenovo/x60/mainboard.c M src/mainboard/roda/rk886ex/devicetree.cb M src/southbridge/intel/i82801gx/chip.h 21 files changed, 46 insertions(+), 32 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 358fcf4..833d658 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -55,8 +55,8 @@ register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000"
- register "ide_enable_primary" = "1" - register "ide_enable_secondary" = "1" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "true"
register "c4onc3_enable" = "1"
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 5d10628..846a02b 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -38,7 +38,7 @@ # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "2"
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440"
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index d0759e2..8115430 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -33,7 +33,7 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b"
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440"
register "gen1_dec" = "0x000c0291" # Superio HWM diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index 818ceaa..ef019d1 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -33,7 +33,7 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b"
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440"
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 9f4142b..4237041 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -31,7 +31,7 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b"
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440"
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index e0df76b..23268f2b 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -33,7 +33,7 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b"
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440"
register "gen1_dec" = "0x000c0291" # Superio HWM diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index ad9b961..a9cad93 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -38,8 +38,8 @@
register "gpe0_en" = "0"
- register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false"
register "p_cnt_throttling_supported" = "0"
diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index 82b1c61..1044851 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -29,7 +29,7 @@ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set)
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x04000440"
register "gen1_dec" = "0x00000295" # HWM diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 578f13d..46bb422 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -31,8 +31,8 @@ register "gpe0_en" = "0x00000441" register "alt_gp_smi_en" = "0x0000"
- register "ide_enable_primary" = "0x0" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "false" + register "ide_enable_secondary" = "false" register "sata_ports_implemented" = "0x3"
register "gen1_dec" = "0x003c0a01" # Super I/O EC and GPIO diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 345bbd8..2514ad4 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -43,8 +43,8 @@ register "alt_gp_smi_en" = "0x0100"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false"
register "c3_latency" = "85" register "docking_supported" = "1" diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 28af26f..673172d 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -61,8 +61,8 @@
register "gpe0_en" = "0"
- register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index d216863..3a4ae45 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -32,8 +32,8 @@ register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x40"
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 1b59fcc..51ca420 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -34,8 +34,8 @@ # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1"
- register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false"
register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 0238e04..5c72c72 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -36,8 +36,8 @@ register "gpi13_routing" = "1" register "gpe0_en" = "0x20000601"
- register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0"
diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 9e5c136..641ada5 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -50,7 +50,7 @@ register "gpi14_routing" = "2" register "gpi15_routing" = "2"
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440"
register "gen1_dec" = "0x00fc0a01" # HWM diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 90da56c..e58d8f3 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -35,8 +35,8 @@ register "gpi13_routing" = "1"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x1" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "true" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0"
diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 7ebe25e..5b38ec2 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -34,7 +34,7 @@ } else if (idedev && idedev->chip_info && h8_ultrabay_device_present()) { config = idedev->chip_info; - config->ide_enable_primary = 1; + config->ide_enable_primary = true; pmh7_ultrabay_power_enable(1); ec_write(0x0c, 0x84); } else { diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index a4b9ac8..9a2c452 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -31,7 +31,7 @@ # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1" # ??vendor
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440"
register "gen1_dec" = "0x00fc0a01" diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 2eb0c38..238d949 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -37,7 +37,7 @@ idedev = pcidev_on_root(0x1f, 1); if (idedev && idedev->chip_info && dock_ultrabay_device_present()) { struct southbridge_intel_i82801gx_config *config = idedev->chip_info; - config->ide_enable_primary = 1; + config->ide_enable_primary = true; /* enable Ultrabay power */ outb(inb(0x1628) | 0x01, 0x1628); ec_write(0x0c, 0x84); diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 4023af80..eb0bdcd 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -46,8 +46,8 @@ register "p_cnt_throttling_supported" = "1"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false"
register "gen1_dec" = "0x001c02e1" # COM3, COM4 register "gen2_dec" = "0x00fc0601" # ?? diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 09a7126..ba8dd6f 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -55,8 +55,8 @@ uint16_t alt_gp_smi_en;
/* IDE configuration */ - uint32_t ide_enable_primary; - uint32_t ide_enable_secondary; + bool ide_enable_primary; + bool ide_enable_secondary; enum sata_mode sata_mode; uint32_t sata_ports_implemented;
-
Felix Held (Code Review)