Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35676 )
Change subject: intel/i945: Delay bridge VGA IO enable to ramstage ......................................................................
intel/i945: Delay bridge VGA IO enable to ramstage
Change-Id: Ifc54ecc96b6d9d79d5a16b2d7baeae70b59275c9 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/northbridge/intel/i945/early_init.c 1 file changed, 0 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/35676/1
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 791baec..c53577b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -661,11 +661,6 @@ reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN); reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32); - - /* Set VGA enable bit in PCIe bridge */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_VGA; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); }
/* Enable GPEs */
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35676 )
Change subject: intel/i945: Delay bridge VGA IO enable to ramstage ......................................................................
Patch Set 1: Code-Review+2
So set_vga_bridge_bits() will enable VGA decode on the last external PCI_CLASS_DISPLAY_VGA found? If so this seems like a good change as it looks like multiple PCI bridges could get VGA decode enabled...
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35676 )
Change subject: intel/i945: Delay bridge VGA IO enable to ramstage ......................................................................
intel/i945: Delay bridge VGA IO enable to ramstage
Change-Id: Ifc54ecc96b6d9d79d5a16b2d7baeae70b59275c9 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35676 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/i945/early_init.c 1 file changed, 0 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 791baec..c53577b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -661,11 +661,6 @@ reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN); reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32); - - /* Set VGA enable bit in PCIe bridge */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_VGA; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); }
/* Enable GPEs */
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)