Change in coreboot[master]: mb/google/dedede/var/driblee: Configure thermal sensor setting

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57091 )

Change subject: mb/google/dedede/var/driblee: Configure thermal sensor setting
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mb/google/dedede/var/driblee: Configure thermal sensor setting

According to schematics, TSR2 thermal sensor is not present in driblee.

BUG=b:191732473, b:197180925, b:195868075
BRANCH=keeby
TEST=FW_NAME="driblee" emerge-keeby coreboot

Signed-off-by: Frank Wu 
Change-Id: I343a6161f71f66b77d23f1fa2f581aaee5eddf1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57091
Reviewed-by: EricR Lai 
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Shou-Chieh Hsu 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/dedede/variants/driblee/overridetree.cb
1 file changed, 36 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Karthik Ramasubramanian: Looks good to me, approved
  EricR Lai: Looks good to me, approved
  Shou-Chieh Hsu: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/dedede/variants/driblee/overridetree.cb b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
index 4b0987f..083e515 100644
--- a/src/mainboard/google/dedede/variants/driblee/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
@@ -41,6 +41,42 @@
    register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0"

device domain 0 on
+		device pci 04.0 on
+			chip drivers/intel/dptf
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU, CPU,           90, 10000),
+					[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
+					[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000)
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,           105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)
+				}"
+
+				## Power Limits Control
+				register "controls.power_limits" = "{
+					.pl1 = {
+						.min_power = 3000,
+						.max_power = 6000,
+						.time_window_min = 1 * MSECS_PER_SEC,
+						.time_window_max = 1 * MSECS_PER_SEC,
+						.granularity = 200,
+					},
+					.pl2 = {
+						.min_power = 20000,
+						.max_power = 20000,
+						.time_window_min = 1 * MSECS_PER_SEC,
+						.time_window_max = 1 * MSECS_PER_SEC,
+						.granularity = 1000,
+					}
+				}"
+				device generic 0 on end
+			end
+		end # SA Thermal device
    	device pci 14.0 on
    		chip drivers/usb/acpi
    			device usb 0.0 on