Patch set updated for coreboot: nb/x4x: Fix raminit unconditionally resetting

[Arthur Heymans]

Arthur Heymans ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17659

-gerrit

commit 8708316b3599f4e447bb819895a6e98d96802446
Author: Arthur Heymans 
Date:   Wed Nov 30 18:40:38 2016 +0100

nb/x4x: Fix raminit unconditionally resetting

The raminit only succeeds when it starts from a cold boot.
    To achieve this it unconditionally did a cold reset.
    This patch uses the sticky scratchpad MCHBAR to issue a cold reset
    only when not started from a cold boot.

It also adds a 2s delay before reset because some disk drives
    expect a warm reboot when the OS wants to reboot and therefore are not
    shut down properly / in time. If the drive is unexpectedly powered off
    which happens during a cold reset, it can cause data loss. Giving the
    drive 2 extra seconds can work around this issue.
    (A proper fix would be to fix the raminit such that it works on a hot reset)

Change-Id: I6063dd6aed908558155d2523f35d7241ff1f4fde
    Signed-off-by: Arthur Heymans 
---
 src/northbridge/intel/x4x/raminit_ddr2.c | 11 +++++++++--
 src/northbridge/intel/x4x/x4x.h          |  4 +---
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index b3ee34a..bfc918e 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -259,9 +259,15 @@ static void checkreset_ddr2(struct sysinfo *s)
    u8 pmcon2;
    u8 reset = 0;

+	if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE)) {
+		printk(BIOS_DEBUG, "Waiting for disks to timeout...\n");
+		mdelay(2000);
+		reset = 1;
+	}
+
    pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
-	if (!(pmcon2 & 0x80)) {
-		pmcon2 |= 0x80;
+	if (pmcon2 & 0x80) {
+		pmcon2 &= ~0x80;
    	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
    	reset = 1;

@@ -2058,4 +2064,5 @@ void raminit_ddr2(struct sysinfo *s)
    MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26);

printk(BIOS_DEBUG, "Done ddr2\n");
+	MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
 }
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index e4eb8dd..f9c5497 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -97,9 +97,7 @@
 #define CLKCFG_MEMCLK_MASK	(7 << CLKCFG_MEMCLK_SHIFT)
 #define CLKCFG_UPDATE		(1 << 12)

-#define SSKPD_MCHBAR		0x0c1c
-#define SSKPD_CLK_SHIFT		0
-#define SSKPD_CLK_MASK		(7 << SSKPD_CLK_SHIFT)
+#define SSKPD_MCHBAR		0x0c20

/*
  * DMIBAR