EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39495 )
Change subject: lib/spd_bin: Add LPDDR4X,DDR5 and LPDDR5 SPD information ......................................................................
lib/spd_bin: Add LPDDR4X,DDR5 and LPDDR5 SPD information
Follow JESD 21-C: DDR4 SPD Document Release 4 to add new DDR type.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I455c9e4c884ae74c72572be6dc2bd281a660e517 --- M src/include/spd_bin.h M src/lib/spd_bin.c 2 files changed, 13 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39495/1
diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index c78f7c3..fb771f2 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -29,6 +29,9 @@ #define SPD_DRAM_LPDDR3_JEDEC 0x0F #define SPD_DRAM_DDR4 0x0C #define SPD_DRAM_LPDDR4 0x10 +#define SPD_DRAM_LPDDR4X 0x11 +#define SPD_DRAM_DDR5 0x12 +#define SPD_DRAM_LPDDR5 0x13 #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define DDR3_ORGANIZATION 7 diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 35bcb4c..625eec8 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -36,10 +36,13 @@ case SPD_DRAM_DDR3: case SPD_DRAM_LPDDR3_INTEL: return false; - /* LPDDR3, LPDDR4 and DDR4 share the same attributes */ + /* Below DDR type share the same attributes */ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_LPDDR4: + case SPD_DRAM_LPDDR4X: + case SPD_DRAM_DDR5: + case SPD_DRAM_LPDDR5: return true; default: printk(BIOS_ERR, "Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n", @@ -60,6 +63,12 @@ return "DDR4"; case SPD_DRAM_LPDDR4: return "LPDDR4"; + case SPD_DRAM_LPDDR4X: + return "LPDDR4X"; + case SPD_DRAM_DDR5: + return "DDR5"; + case SPD_DRAM_LPDDR5: + return "LPDDR5"; } return "UNKNOWN"; }
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39495 )
Change subject: lib/spd_bin: Add LPDDR4X,DDR5 and LPDDR5 SPD information ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39495/1/src/lib/spd_bin.c File src/lib/spd_bin.c:
https://review.coreboot.org/c/coreboot/+/39495/1/src/lib/spd_bin.c@44 PS1, Line 44: case SPD_DRAM_DDR5: : case SPD_DRAM_LPDDR5: Can you please point me to the JEDEC spec where this is captured? I couldn't find any more information about SPD for DDR5/LPDDR5 except their ids.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39495 )
Change subject: lib/spd_bin: Add LPDDR4X,DDR5 and LPDDR5 SPD information ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39495/1/src/lib/spd_bin.c File src/lib/spd_bin.c:
https://review.coreboot.org/c/coreboot/+/39495/1/src/lib/spd_bin.c@44 PS1, Line 44: case SPD_DRAM_DDR5: : case SPD_DRAM_LPDDR5:
Can you please point me to the JEDEC spec where this is captured? I couldn't find any more informati […]
Yes, just ids. And we assume that use ddr4 until we have details. Or where should I put it?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39495 )
Change subject: lib/spd_bin: Add LPDDR4X,DDR5 and LPDDR5 SPD information ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39495/1/src/lib/spd_bin.c File src/lib/spd_bin.c:
https://review.coreboot.org/c/coreboot/+/39495/1/src/lib/spd_bin.c@44 PS1, Line 44: case SPD_DRAM_DDR5: : case SPD_DRAM_LPDDR5:
Yes, just ids. And we assume that use ddr4 until we have details. […]
I think we can add those as and when required. Currently, nothing is using it.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39495 )
Change subject: lib/spd_bin: Add LPDDR4X,DDR5 and LPDDR5 SPD information ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39495/1/src/lib/spd_bin.c File src/lib/spd_bin.c:
https://review.coreboot.org/c/coreboot/+/39495/1/src/lib/spd_bin.c@44 PS1, Line 44: case SPD_DRAM_DDR5: : case SPD_DRAM_LPDDR5:
I think we can add those as and when required. Currently, nothing is using it.
okay, I will remove it. Since it under developing. I think still can keep the ids in the patch.
Hello build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39495
to look at the new patch set (#2).
Change subject: lib/spd_bin: Add LPDDR4X SPD information and DDR5, LPDDR5 IDs ......................................................................
lib/spd_bin: Add LPDDR4X SPD information and DDR5, LPDDR5 IDs
Follow JESD 21-C: DDR4 SPD Document Release 4 to add new DDR type.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I455c9e4c884ae74c72572be6dc2bd281a660e517 --- M src/include/spd_bin.h M src/lib/spd_bin.c 2 files changed, 11 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39495/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39495 )
Change subject: lib/spd_bin: Add LPDDR4X SPD information and DDR5, LPDDR5 IDs ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39495 )
Change subject: lib/spd_bin: Add LPDDR4X SPD information and DDR5, LPDDR5 IDs ......................................................................
lib/spd_bin: Add LPDDR4X SPD information and DDR5, LPDDR5 IDs
Follow JESD 21-C: DDR4 SPD Document Release 4 to add new DDR type.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I455c9e4c884ae74c72572be6dc2bd281a660e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39495 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/include/spd_bin.h M src/lib/spd_bin.c 2 files changed, 11 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index c78f7c3..fb771f2 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -29,6 +29,9 @@ #define SPD_DRAM_LPDDR3_JEDEC 0x0F #define SPD_DRAM_DDR4 0x0C #define SPD_DRAM_LPDDR4 0x10 +#define SPD_DRAM_LPDDR4X 0x11 +#define SPD_DRAM_DDR5 0x12 +#define SPD_DRAM_LPDDR5 0x13 #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define DDR3_ORGANIZATION 7 diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 35bcb4c..f59e187 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -36,10 +36,11 @@ case SPD_DRAM_DDR3: case SPD_DRAM_LPDDR3_INTEL: return false; - /* LPDDR3, LPDDR4 and DDR4 share the same attributes */ + /* Below DDR type share the same attributes */ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_LPDDR4: + case SPD_DRAM_LPDDR4X: return true; default: printk(BIOS_ERR, "Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n", @@ -60,6 +61,12 @@ return "DDR4"; case SPD_DRAM_LPDDR4: return "LPDDR4"; + case SPD_DRAM_LPDDR4X: + return "LPDDR4X"; + case SPD_DRAM_DDR5: + return "DDR5"; + case SPD_DRAM_LPDDR5: + return "LPDDR5"; } return "UNKNOWN"; }