Change in ...coreboot[master]: soc/intel/cannonlake: Disable PCH thermal sensor check during S0ix
Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33292 Change subject: soc/intel/cannonlake: Disable PCH thermal sensor check during S0ix ...................................................................... soc/intel/cannonlake: Disable PCH thermal sensor check during S0ix This disables PCH thermal sensor check during system entry in S0ix state. BUG=133345634 BRANCH=None TEST=Verified S0ix entry with Thermal sensor disabled. Change-Id: I298079e91bfea87ba02a8a32a622f2b0bbfc31a6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> --- M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/include/soc/pmc.h 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/33292/1 diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 4dfd15b..b2f3d48 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -81,7 +81,7 @@ /* Disable XTAL shutdown qualification for low power idle. */ if (config->s0ix_enable) { reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; + reg32 |= (XTALSDQDIS | TSDQDIS); write32(pmcbase + CPPMVRIC, reg32); } diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 67854d4..b4110cf 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -150,6 +150,7 @@ #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) +#define TSDQDIS (1 << 26) #define IRQ_REG ACTL #define SCI_IRQ_ADJUST 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/33292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298079e91bfea87ba02a8a32a622f2b0bbfc31a6 Gerrit-Change-Number: 33292 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Gerrit-MessageType: newchange
Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33292 to look at the new patch set (#2). Change subject: [TEST] soc/intel/cannonlake: Disable PCH thermal sensor check during S0ix ...................................................................... [TEST] soc/intel/cannonlake: Disable PCH thermal sensor check during S0ix This disables PCH thermal sensor check during system entry in S0ix state. BUG=133345634 BRANCH=None TEST=Verified S0ix entry with Thermal sensor disabled. Change-Id: I298079e91bfea87ba02a8a32a622f2b0bbfc31a6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> --- M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/include/soc/pmc.h 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/33292/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/33292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298079e91bfea87ba02a8a32a622f2b0bbfc31a6 Gerrit-Change-Number: 33292 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-MessageType: newpatchset
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33292 ) Change subject: [TEST] soc/intel/cannonlake: Disable PCH thermal sensor check during S0ix ...................................................................... Patch Set 2: This is being tested on Arcada (WHL) systems and works fine. This is one of the alternate solution for system entering into S0ix state. -- To view, visit https://review.coreboot.org/c/coreboot/+/33292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298079e91bfea87ba02a8a32a622f2b0bbfc31a6 Gerrit-Change-Number: 33292 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Thu, 13 Jun 2019 11:48:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33292 ) Change subject: [TEST] soc/intel/cannonlake: Disable PCH thermal sensor check during S0ix ...................................................................... Patch Set 2: (1 comment) This seems better than just setting a higher threshold to ensure s0ix is not aborted. https://review.coreboot.org/#/c/33292/2/src/soc/intel/cannonlake/include/soc... File src/soc/intel/cannonlake/include/soc/pmc.h: https://review.coreboot.org/#/c/33292/2/src/soc/intel/cannonlake/include/soc... PS2, Line 153: nit: the rest of the file uses a single space after the #define and not a tab -- To view, visit https://review.coreboot.org/c/coreboot/+/33292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298079e91bfea87ba02a8a32a622f2b0bbfc31a6 Gerrit-Change-Number: 33292 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Thu, 13 Jun 2019 17:52:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33292?usp=email ) Change subject: [TEST] soc/intel/cannonlake: Disable PCH thermal sensor check during S0ix ...................................................................... Abandoned This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author. -- To view, visit https://review.coreboot.org/c/coreboot/+/33292?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298079e91bfea87ba02a8a32a622f2b0bbfc31a6 Gerrit-Change-Number: 33292 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> Gerrit-Reviewer: Duncan L Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh@gmail.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Martin L Roth <gaumless@gmail.com> Gerrit-MessageType: abandon
participants (3)
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Duncan Laurie (Code Review) -
Martin L Roth (Code Review)
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Sumeet R Pawnikar (Code Review)