Sumeet R Pawnikar has uploaded this change for review.
soc/intel/cannonlake: Disable PCH thermal sensor check during S0ix
This disables PCH thermal sensor check during system entry in S0ix state.
BUG=133345634
BRANCH=None
TEST=Verified S0ix entry with Thermal sensor disabled.
Change-Id: I298079e91bfea87ba02a8a32a622f2b0bbfc31a6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
---
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/cannonlake/include/soc/pmc.h
2 files changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/33292/1
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index 4dfd15b..b2f3d48 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -81,7 +81,7 @@
/* Disable XTAL shutdown qualification for low power idle. */
if (config->s0ix_enable) {
reg32 = read32(pmcbase + CPPMVRIC);
- reg32 |= XTALSDQDIS;
+ reg32 |= (XTALSDQDIS | TSDQDIS);
write32(pmcbase + CPPMVRIC, reg32);
}
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h
index 67854d4..b4110cf 100644
--- a/src/soc/intel/cannonlake/include/soc/pmc.h
+++ b/src/soc/intel/cannonlake/include/soc/pmc.h
@@ -150,6 +150,7 @@
#define CPPMVRIC 0x1B1C
#define XTALSDQDIS (1 << 22)
+#define TSDQDIS (1 << 26)
#define IRQ_REG ACTL
#define SCI_IRQ_ADJUST 0
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