Patch set updated for coreboot: FSP2.0: Add MemoryInit API

[Andrey Petrov]

Andrey Petrov ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13798

-gerrit

commit e669c0807efdbcf40e9d7af14026330167eeb664
Author: Andrey Petrov 
Date:   Thu Feb 25 14:16:33 2016 -0800

FSP2.0: Add MemoryInit API

This adds implementation of fsp_memory_init() that is used to train
    memory.

Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979
    Signed-off-by: Andrey Petrov 
---
 src/drivers/intel/fsp2_0/memory_init.c | 100 +++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
new file mode 100644
index 0000000..74ec2c6
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov  for Intel Corp.)
+ * (Written by Alexandru Gagniuc  for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/io.h>
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <memrange.h>
+#include <string.h>
+#include <timestamp.h>
+
+struct fsp_memory_init_params {
+	void *nvs_buffer;
+	void *raminit_upd;
+	void **hob_list;
+} __attribute__ ((__packed__));
+
+typedef asmlinkage enum fsp_status (*fsp_memory_init_fn)
+				   (struct fsp_memory_init_params *);
+
+static struct FSP_M_CONFIG *fsp_parse_m_upd(void *cfg_region,
+					    struct fsp_m_arch_upd *arch_upd)
+{
+	uint8_t *raw_hdr = (uint8_t*) cfg_region;
+
+	/* M_ARCH_UPD starts at 0x20 offset */
+	raw_hdr += 0x20;
+
+	arch_upd->revision = read8(raw_hdr + 0x20);
+	arch_upd->nvs_buffer = read32(raw_hdr + 0x24);
+	arch_upd->stack_base = read32(raw_hdr + 0x28);
+	arch_upd->stack_size = read32(raw_hdr + 0x2c);
+	arch_upd->bootloader_tolumsz = read32(raw_hdr + 0x30);
+	arch_upd->boot_mode = read32(raw_hdr + 0x34);
+
+	return (struct FSP_M_CONFIG *) read32(raw_hdr + 0x20);
+}
+
+static enum fsp_status do_fsp_memory_init(void **hob_list_ptr,
+					  struct fsp_header *hdr)
+{
+	enum fsp_status status;
+	fsp_memory_init_fn fsp_raminit;
+	struct fsp_memory_init_params raminit_params;
+	struct fsp_m_arch_upd arch_upd;
+	struct FSP_M_CONFIG *m_config;
+	void *cfg_region;
+
+	post_code(0x34);
+	/* UPD region resides in CAR. Thus, it can be directly modified. */
+	cfg_region = (void *)(hdr->cfg_region_offset + hdr->image_base);
+
+	/* Read default values from arch_upd, perhaps they can be useful. */
+	m_config = fsp_parse_m_upd(cfg_region, &arch_upd);
+
+	/* Get any board specific changes */
+	raminit_params.nvs_buffer = NULL;
+	raminit_params.raminit_upd = cfg_region;
+	raminit_params.hob_list = hob_list_ptr;
+
+	/* Update the UPD data */
+	platform_fsp_memory_init_params_cb(&arch_upd, m_config);
+
+	/* Call FspMemoryInit */
+	fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
+	printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit);
+	printk(BIOS_SPEW, "\t%p: nvs_buffer\n", raminit_params.nvs_buffer);
+	printk(BIOS_SPEW, "\t%p: raminit_upd\n", raminit_params.raminit_upd);
+	printk(BIOS_SPEW, "\t%p: hob_list\n", raminit_params.hob_list);
+
+	timestamp_add_now(TS_FSP_MEMORY_INIT_START);
+	status = fsp_raminit(&raminit_params);
+	post_code(0x37);
+	timestamp_add_now(TS_FSP_MEMORY_INIT_END);
+
+	printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
+
+	return status;
+}
+
+enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *range)
+{
+	struct fsp_header hdr;
+
+	if (fsp_load_binary(&hdr, CONFIG_FSP_M_FILE, range) != CB_SUCCESS)
+		return FSP_NOT_FOUND;
+
+	return do_fsp_memory_init(hob_list, &hdr);
+}