Change in coreboot[master]: soc/intel/ehl/fsp_params: Set Intel Speed Step (Eist) from devicetree

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63352 )

Change subject: soc/intel/ehl/fsp_params: Set Intel Speed Step (Eist) from devicetree
......................................................................

soc/intel/ehl/fsp_params: Set Intel Speed Step (Eist) from devicetree

This patch provides the set value for intel speed step in devicetree
for FSPS. Before that in case of not set value in device tree the
default value of disabled was overwritten by default enabled of FSP.

Test: mainboard/siemens/mc_ehl/variants/mc_ehl1
Check status of Bit 16 in MSR 0x1a0 after boot.

Change-Id: I0a5ef4968a27978116c21ce35b3818c6b36e086f
Signed-off-by: Uwe Poeche 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63352
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/soc/intel/elkhartlake/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index 1584c6a..2100cc4 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -264,6 +264,9 @@
    params->DdiPortCHpd = config->DdiPortCHpd;
    params->DdiPortCDdc = config->DdiPortCDdc;

+	/* Intel Speed Step */
+	params->Eist = config->eist_enable;
+
    /* Use coreboot MP PPI services if Kconfig is enabled */
    if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
    	params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();