Change in coreboot[master]: src/soc/intel/skl: Add AML IccMax and show IGD SKU

[Gaggery Tsai (Code Review)]

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/27610

Change subject: src/soc/intel/skl: Add AML IccMax and show IGD SKU
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src/soc/intel/skl: Add AML IccMax and show IGD SKU

This patch adds AML IccMax for VR configuration. From doc #594883, the
IccMax for Core was changed to 28A, we need this patch to accommodate
the changes. Besides, add up AML-Y GFX sku ID while reporting system
information.

BUG=None
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage
     I will need a AML device to test. WIP.

Change-Id: Ic22bae162b58b06b9519f1b708be55bde5e4641e
Signed-off-by: Gaggery Tsai 
---
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/vr_config.c
2 files changed, 22 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/27610/1

diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c
index 7d5bc3f..1072236 100644
--- a/src/soc/intel/skylake/bootblock/report_platform.c
+++ b/src/soc/intel/skylake/bootblock/report_platform.c
@@ -102,6 +102,7 @@
    { PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, "Kabylake-R ULT GT2"},
    { PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, "Kabylake HALO GT2" },
    { PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, "Kabylake DT GT2" },
+	{ PCI_DEVICE_ID_INTEL_KBL_GT2_ULX_R, "Amberlake ULX GT2" },
 };

static uint8_t get_dev_revision(pci_devfn_t dev)
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index 57affe5..6a1f3e5 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -23,6 +23,7 @@

#define KBLY_ICCMAX_SA					VR_CFG_AMP(4.1)
 #define KBLY_ICCMAX_CORE				VR_CFG_AMP(24)
+#define AMLY_ICCMAX_CORE				VR_CFG_AMP(28)
 #define KBLY_ICCMAX_GTS_GTUS			VR_CFG_AMP(24)
 #define KBLR_ICCMAX_SA_U42				VR_CFG_AMP(6)
 #define KBLU_ICCMAX_SA_U22				VR_CFG_AMP(4.5)
@@ -36,11 +37,13 @@
    KBL_R_SKU,
    KBL_U_BASE_SKU,
    KBL_U_PREMIUM_SKU,
+	AML_Y_SKU,
 };

/*
  * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the
  * Iccmax is the same among KBL-Y but KBL-U/R.
+ * Addendum for AML-Y #594883, IccMax for IA core is 28A.
  * +----------------+-------------+---------------+------+-----+
  * | Domain/Setting |  SA         |  IA           | GTUS | GTS |
  * +----------------+-------------+---------------+------+-----+
@@ -50,6 +53,8 @@
  * +----------------+-------------+---------------+------+-----+
  * | IccMax(KBL-Y)  | 4.1A        | 24A           | 24A  | 24A |
  * +----------------+-------------+---------------+------+-----+
+ * | IccMax(AML-Y)  | 4.1A        | 28A           | 24A  | 24A |
+ * +----------------+-------------+---------------+------+-----+
  */

static const struct {
@@ -92,6 +97,15 @@
    		KBLUR_ICCMAX_GTS_GTUS
    	}
    },
+	[AML_Y_SKU] = {
+		.sku = AML_Y_SKU,
+		.icc_max = {
+			KBLY_ICCMAX_SA,
+			AMLY_ICCMAX_CORE,
+			KBLY_ICCMAX_GTS_GTUS,
+			KBLY_ICCMAX_GTS_GTUS
+		}
+	},
 };

/* Default values for domain configuration. PSI3 and PSI4 are disabled. */
@@ -176,9 +190,13 @@
    id = get_dev_id(SA_DEV_ROOT);
    if (id == PCI_DEVICE_ID_INTEL_KBL_U_R)
    	sku = KBL_R_SKU;
-	else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y)
-		sku = KBL_Y_SKU;
-	else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_U) {
+	else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y) {
+		id = get_dev_id(SA_DEV_IGD);
+		if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_ULX_R)
+			sku = AML_Y_SKU;
+		else
+			sku = KBL_Y_SKU;
+	} else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_U) {
    	id = get_dev_id(PCH_DEV_LPC);
    	if (id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22)
    		sku = KBL_U_BASE_SKU;