Change in coreboot[master]: security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()` - coreboot-gerrit

4 Jun 2021


      Attention is currently required from: Andrey Pronin, Christian Walter, Aseda Aboagye, Aaron Durbin.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55241 )
Change subject: security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()`
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Patch Set 1:
(1 comment)
File src/security/tpm/tss/tcg-2.0/tss.c:
https://review.coreboot.org/c/coreboot/+/55241/comment/3ff0bd27_7b8adbab 
PS1, Line 333: 	printk(BIOS_INFO, "%s: response is %x\n",
Should that be more debug level? Please paste some of these lines from your device  to the commit messages too. I see, it’s done elsewhere too, but for me this needs to be fixed to be debug.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I6ca6376bb9f7ed8fd1167c2c80f1e8d3c3f46653
Gerrit-Change-Number: 55241
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