Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/27468
Change subject: soc/intel/coffeelake: Add initial coffeelake support ......................................................................
soc/intel/coffeelake: Add initial coffeelake support
Add coffeelake config and include path to coffeelake fsp header files.
BUG=N/A TEST=Using private mainboard file can boot up on coffeelake rvp platform.
Change-Id: Ide180de32a9d1896bed85b9e093963721c3d6041 Signed-off-by: Lijian Zhao lijian.zhao@intel.com --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc 2 files changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27468/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 101d71e..fea6bb3 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -3,6 +3,13 @@ help Intel Cannonlake support
+config SOC_INTEL_COFFEELAKE + bool + default n + select SOC_INTEL_CANNONLAKE + help + Intel Coffeelake support + if SOC_INTEL_CANNONLAKE
config CPU_SPECIFIC_OPTIONS @@ -71,6 +78,7 @@ select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO
+ config UART_FOR_CONSOLE int "Index for LPSS UART port to use for console" default 2 if DRIVERS_UART_8250MEM_32 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index f8f9198..0a09eb6 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -73,8 +73,11 @@ verstage-y += spi.c verstage-$(CONFIG_UART_DEBUG) += uart.c
-CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20 +ifeq ($(CONFIG_SOC_INTEL_COFFEELAKE),y) +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/coffeelake +else CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake +endif
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include
-
Lijian Zhao (Code Review)