Change in ...coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init

[Frans Hendriks (Code Review)]

Hello David Hendricks, Paul Menzel, build bot (Jenkins), Hannah Williams, Michał Żygowski,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/28464

to look at the new patch set (#3).

Change subject: drivers/intel/fsp1_1: Configure UART after memory init
......................................................................

drivers/intel/fsp1_1: Configure UART after memory init

FSP code will default enable the onboard serial port.
When external serial port is used, this onboard port needs to be
disabled.

Add function mainboard_after_memory_init() function to perform
required actions to re-enabled output to external serial port.

BUG=N/A
TEST=LPC Post card on Intel Cherry Hill

Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d
Signed-off-by: Frans Hendriks 
---
M src/drivers/intel/fsp1_1/include/fsp/romstage.h
M src/drivers/intel/fsp1_1/raminit.c
2 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28464/3