Change in coreboot[master]: nb/intel/sandybridge: Make the mainboard_rcba_config hook optional
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36781 )
Change subject: nb/intel/sandybridge: Make the mainboard_rcba_config hook optional ......................................................................
nb/intel/sandybridge: Make the mainboard_rcba_config hook optional
This also changes the name to mainboard_late_rcba_config to better reflect what it does.
This adds an empty weakly linked default. The rationale behind this change is that without the callback some features might not work but that the result is likely still able to boot, so it can be made optional.
Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/apple/macbookair4_2/romstage.c M src/mainboard/asrock/b75pro3-m/romstage.c M src/mainboard/asus/h61m-cs/romstage.c M src/mainboard/asus/maximus_iv_gene-z/romstage.c M src/mainboard/asus/p8h61-m_lx/romstage.c M src/mainboard/asus/p8h61-m_pro/romstage.c M src/mainboard/asus/p8z77-m_pro/romstage.c M src/mainboard/compulab/intense_pc/romstage.c M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/hp/2570p/romstage.c M src/mainboard/hp/2760p/romstage.c M src/mainboard/hp/8460p/romstage.c M src/mainboard/hp/8470p/romstage.c M src/mainboard/hp/8770w/romstage.c M src/mainboard/hp/compaq_8200_elite_sff/romstage.c M src/mainboard/hp/folio_9470m/romstage.c M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/hp/z220_sff_workstation/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x131e/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/msi/ms7707/romstage.c M src/mainboard/roda/rv11/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/sapphire/pureplatinumh61/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/pch.h 45 files changed, 23 insertions(+), 130 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/36781/1
diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/romstage.c index a7c543d..5522ea0 100644 --- a/src/mainboard/apple/macbookair4_2/romstage.c +++ b/src/mainboard/apple/macbookair4_2/romstage.c @@ -27,7 +27,7 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Disable devices. */ RCBA32(0x3414) = 0x00000020; diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c index fe6d183..fe1416b 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/romstage.c @@ -27,10 +27,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/romstage.c index 37b07e5..4c8eda7 100644 --- a/src/mainboard/asus/h61m-cs/romstage.c +++ b/src/mainboard/asus/h61m-cs/romstage.c @@ -31,10 +31,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/romstage.c index 6cf206b..e29dd0f 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/romstage.c +++ b/src/mainboard/asus/maximus_iv_gene-z/romstage.c @@ -44,10 +44,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - void mainboard_config_superio(void) { static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/romstage.c index 5f94d17..01ae603 100644 --- a/src/mainboard/asus/p8h61-m_lx/romstage.c +++ b/src/mainboard/asus/p8h61-m_lx/romstage.c @@ -47,10 +47,6 @@ CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); }
-void mainboard_rcba_config(void) -{ -} - void mainboard_config_superio(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/romstage.c index 60d311d..3736ab6 100644 --- a/src/mainboard/asus/p8h61-m_pro/romstage.c +++ b/src/mainboard/asus/p8h61-m_pro/romstage.c @@ -32,10 +32,6 @@ KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/asus/p8z77-m_pro/romstage.c b/src/mainboard/asus/p8z77-m_pro/romstage.c index db2d303..5fff2e1 100644 --- a/src/mainboard/asus/p8z77-m_pro/romstage.c +++ b/src/mainboard/asus/p8z77-m_pro/romstage.c @@ -34,10 +34,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { /* {enable, current, oc_pin} */ { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */ diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 8198d8a..f44a7e8 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -39,7 +39,7 @@ #endif }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { RCBA32(0x3414) = 0x00000000; } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index f67d51b..25e1d03 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -87,7 +87,7 @@ read_spd(&spd[3], 0x53, id_only); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Enable HECI */ RCBA32(FD2) &= ~0x2; diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c index 1df5bfd..57cc070 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c @@ -27,10 +27,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 449ccf5..3aef9d0 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -35,7 +35,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32;
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index d42572b..628e2a0 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -39,7 +39,7 @@ GAMEL_LPC_EN | COMA_LPC_EN); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* * GFX INTA -> PIRQA (MSI) diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 8893819..604cf7b 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -30,7 +30,7 @@ { }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32;
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 6690c68..cbbae2e 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -43,7 +43,7 @@ CNF1_LPC_EN | FDD_LPC_EN); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32;
diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c index 4f7ca3a..8d36f6b 100644 --- a/src/mainboard/hp/2570p/romstage.c +++ b/src/mainboard/hp/2570p/romstage.c @@ -24,10 +24,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 0, 1, 0 }, diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c index a696fae..5bf8789 100644 --- a/src/mainboard/hp/2760p/romstage.c +++ b/src/mainboard/hp/2760p/romstage.c @@ -23,10 +23,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 1, 1, 0 }, diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c index 77c355b..397810e 100644 --- a/src/mainboard/hp/8460p/romstage.c +++ b/src/mainboard/hp/8460p/romstage.c @@ -27,10 +27,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* USB0, eSATA */ { 1, 0, 0 }, /* USB charger */ diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c index 890e65b..513b375 100644 --- a/src/mainboard/hp/8470p/romstage.c +++ b/src/mainboard/hp/8470p/romstage.c @@ -26,10 +26,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 1, 1, 0 }, diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c index 49a5b1a..d3034fb 100644 --- a/src/mainboard/hp/8770w/romstage.c +++ b/src/mainboard/hp/8770w/romstage.c @@ -27,10 +27,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* Dock USB3.0 */ { 1, 1, 0 }, /* Conn */ diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c index 90cfcc9..3e726cf 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c @@ -31,10 +31,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, { 1, 0, -1 }, diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c index 3f174a1..969b666 100644 --- a/src/mainboard/hp/folio_9470m/romstage.c +++ b/src/mainboard/hp/folio_9470m/romstage.c @@ -25,10 +25,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* SSP1: dock */ { 1, 1, 0 }, /* SSP2: left, EHCI Debug */ diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c index 8a40578..844bb2f 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -28,7 +28,7 @@ { }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { RCBA32(BUC) = 0x00000000; } diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/romstage.c index bd0a377..2e0a508 100644 --- a/src/mainboard/hp/z220_sff_workstation/romstage.c +++ b/src/mainboard/hp/z220_sff_workstation/romstage.c @@ -31,10 +31,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 7f3a58d..1cd58b0 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -31,7 +31,7 @@ { }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Disable devices */ RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI; diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index e7959ef..16a16de 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -43,11 +43,6 @@ } }
-void mainboard_rcba_config(void) -{ - southbridge_configure_default_intmap(); -} - void mainboard_config_superio(void) { const u16 port = SIO_PORT; diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index f778f96..37713e1 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -43,7 +43,7 @@ COMA_LPC_EN | COMB_LPC_EN); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32;
diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index fc67e5a..37182f8 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -26,10 +26,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, { 1, 0, -1 }, diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 48d26c2..ee1d0ed 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -42,7 +42,7 @@ ec_mm_set_bit(0x3b, 4); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Disable devices. */ RCBA32(BUC) = 0x00000020; diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index e7851f3..7036ec4 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -54,10 +54,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - // OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: system port 4, OC0 */ diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 72cbcad..7b97ff7 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -54,10 +54,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 1, -1 }, /* P0 empty */ { 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */ diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index 3caa443..0cff5d2 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -53,10 +53,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - /* FIXME: used T530 values here */ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 34793d1..298673b 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -24,10 +24,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 75e331e..52898fa 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -56,10 +56,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0 left dual conn, OC 0 */ { 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */ diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index cb17a27..e0b0455 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -56,10 +56,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index 6f176c7..a1d3e88 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -24,10 +24,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index eb2a5b1..f4d2a3c 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -68,10 +68,6 @@ return spd_file + spd_index * 256; }
-void mainboard_rcba_config(void) -{ -} - void mainboard_get_spd(spd_raw_data *spd, bool id_only) { uint8_t *memory; diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 8460208..7989fd6 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -32,10 +32,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 6f10135..3e9ea2c 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -29,10 +29,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */ { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */ diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/romstage.c index 8f83c86..399d44b 100644 --- a/src/mainboard/msi/ms7707/romstage.c +++ b/src/mainboard/msi/ms7707/romstage.c @@ -28,10 +28,6 @@ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xa4, reg16); }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { {1, 0, 0}, {1, 0, 0}, diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/romstage.c index a54a9ad..f168138 100644 --- a/src/mainboard/roda/rv11/romstage.c +++ b/src/mainboard/roda/rv11/romstage.c @@ -16,7 +16,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h>
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32;
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index d4b6dd8..ddcf2ad 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -51,7 +51,7 @@ #endif }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* * GFX INTA -> PIRQA (MSI) diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 77fd160..0665997 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -62,7 +62,7 @@ #endif }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* * GFX INTA -> PIRQA (MSI) diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index 7fcde77..3c9cc82 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -26,7 +26,7 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Disable devices. */ RCBA32(0x3414) = 0x00000020; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 92882b4..c76d2f4 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -34,6 +34,10 @@ { }
+__weak void mainboard_late_rcba_config(void) +{ +} + static void early_pch_reset_pmcon(void) { u8 reg8; @@ -100,7 +104,7 @@
southbridge_configure_default_intmap(); southbridge_rcba_config(); - mainboard_rcba_config(); + mainboard_late_rcba_config();
post_code(0x3d);
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index ac976c2..81d19fa 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -72,7 +72,9 @@ void early_thermal_init(void); void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); -void mainboard_rcba_config(void); +/* Optional mainboard callback to do additional configuration + on the RCBA config space. It is called after the raminit. */ +void mainboard_late_rcba_config(void); void early_pch_init_native(void); void early_pch_init(void); void early_pch_init_native_dmi_pre(void);
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36781 )
Change subject: nb/intel/sandybridge: Make the mainboard_rcba_config hook optional ......................................................................
Patch Set 1: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/36781/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36781/1//COMMIT_MSG@9 PS1, Line 9: late Nice one. Makes it visible that some things in the mb code are actually run too late (e.g. hiding P2P bridge so the MRC doesn't scan it).
https://review.coreboot.org/c/coreboot/+/36781/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/pch.h:
https://review.coreboot.org/c/coreboot/+/36781/1/src/southbridge/intel/bd82x... PS1, Line 75: callback Bothered me more and more, everytime I see it...
Hello Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph, Angel Pons, Tristan Corrick, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36781
to look at the new patch set (#3).
Change subject: nb/intel/sandybridge: Make the mainboard_rcba_config hook optional ......................................................................
nb/intel/sandybridge: Make the mainboard_rcba_config hook optional
This also changes the name to mainboard_late_rcba_config to better reflect what it does.
This adds an empty weakly linked default. The rationale behind this change is that without an implementation of the hook some features might not work but that the result is likely still able to boot, so it can be made optional.
Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/apple/macbookair4_2/romstage.c M src/mainboard/asrock/b75pro3-m/romstage.c M src/mainboard/asus/h61m-cs/romstage.c M src/mainboard/asus/maximus_iv_gene-z/romstage.c M src/mainboard/asus/p8h61-m_lx/romstage.c M src/mainboard/asus/p8h61-m_pro/romstage.c M src/mainboard/asus/p8z77-m_pro/romstage.c M src/mainboard/compulab/intense_pc/romstage.c M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/hp/2570p/romstage.c M src/mainboard/hp/2760p/romstage.c M src/mainboard/hp/8460p/romstage.c M src/mainboard/hp/8470p/romstage.c M src/mainboard/hp/8770w/romstage.c M src/mainboard/hp/compaq_8200_elite_sff/romstage.c M src/mainboard/hp/folio_9470m/romstage.c M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/hp/z220_sff_workstation/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x131e/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/msi/ms7707/romstage.c M src/mainboard/roda/rv11/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/sapphire/pureplatinumh61/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/pch.h 45 files changed, 23 insertions(+), 130 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/36781/3
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36781 )
Change subject: nb/intel/sandybridge: Make the mainboard_rcba_config hook optional ......................................................................
Patch Set 3: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36781 )
Change subject: nb/intel/sandybridge: Make the mainboard_rcba_config hook optional ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36781/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/pch.h:
https://review.coreboot.org/c/coreboot/+/36781/1/src/southbridge/intel/bd82x... PS1, Line 75: callback
Bothered me more and more, everytime I see it...
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36781 )
Change subject: nb/intel/sandybridge: Make the mainboard_rcba_config hook optional ......................................................................
nb/intel/sandybridge: Make the mainboard_rcba_config hook optional
This also changes the name to mainboard_late_rcba_config to better reflect what it does.
This adds an empty weakly linked default. The rationale behind this change is that without an implementation of the hook some features might not work but that the result is likely still able to boot, so it can be made optional.
Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/36781 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/mainboard/apple/macbookair4_2/romstage.c M src/mainboard/asrock/b75pro3-m/romstage.c M src/mainboard/asus/h61m-cs/romstage.c M src/mainboard/asus/maximus_iv_gene-z/romstage.c M src/mainboard/asus/p8h61-m_lx/romstage.c M src/mainboard/asus/p8h61-m_pro/romstage.c M src/mainboard/asus/p8z77-m_pro/romstage.c M src/mainboard/compulab/intense_pc/romstage.c M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/hp/2570p/romstage.c M src/mainboard/hp/2760p/romstage.c M src/mainboard/hp/8460p/romstage.c M src/mainboard/hp/8470p/romstage.c M src/mainboard/hp/8770w/romstage.c M src/mainboard/hp/compaq_8200_elite_sff/romstage.c M src/mainboard/hp/folio_9470m/romstage.c M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/hp/z220_sff_workstation/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x131e/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/msi/ms7707/romstage.c M src/mainboard/roda/rv11/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/sapphire/pureplatinumh61/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/pch.h 45 files changed, 23 insertions(+), 130 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/romstage.c index a7c543d..5522ea0 100644 --- a/src/mainboard/apple/macbookair4_2/romstage.c +++ b/src/mainboard/apple/macbookair4_2/romstage.c @@ -27,7 +27,7 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Disable devices. */ RCBA32(0x3414) = 0x00000020; diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c index fe6d183..fe1416b 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/romstage.c @@ -27,10 +27,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/romstage.c index 37b07e5..4c8eda7 100644 --- a/src/mainboard/asus/h61m-cs/romstage.c +++ b/src/mainboard/asus/h61m-cs/romstage.c @@ -31,10 +31,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/romstage.c index 6cf206b..e29dd0f 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/romstage.c +++ b/src/mainboard/asus/maximus_iv_gene-z/romstage.c @@ -44,10 +44,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - void mainboard_config_superio(void) { static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/romstage.c index 5f94d17..01ae603 100644 --- a/src/mainboard/asus/p8h61-m_lx/romstage.c +++ b/src/mainboard/asus/p8h61-m_lx/romstage.c @@ -47,10 +47,6 @@ CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); }
-void mainboard_rcba_config(void) -{ -} - void mainboard_config_superio(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/romstage.c index 60d311d..3736ab6 100644 --- a/src/mainboard/asus/p8h61-m_pro/romstage.c +++ b/src/mainboard/asus/p8h61-m_pro/romstage.c @@ -32,10 +32,6 @@ KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/asus/p8z77-m_pro/romstage.c b/src/mainboard/asus/p8z77-m_pro/romstage.c index db2d303..5fff2e1 100644 --- a/src/mainboard/asus/p8z77-m_pro/romstage.c +++ b/src/mainboard/asus/p8z77-m_pro/romstage.c @@ -34,10 +34,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { /* {enable, current, oc_pin} */ { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */ diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 8198d8a..f44a7e8 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -39,7 +39,7 @@ #endif }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { RCBA32(0x3414) = 0x00000000; } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index f67d51b..25e1d03 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -87,7 +87,7 @@ read_spd(&spd[3], 0x53, id_only); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Enable HECI */ RCBA32(FD2) &= ~0x2; diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c index 1df5bfd..57cc070 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c @@ -27,10 +27,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 449ccf5..3aef9d0 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -35,7 +35,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32;
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index d42572b..628e2a0 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -39,7 +39,7 @@ GAMEL_LPC_EN | COMA_LPC_EN); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* * GFX INTA -> PIRQA (MSI) diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 8893819..604cf7b 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -30,7 +30,7 @@ { }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32;
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 6690c68..cbbae2e 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -43,7 +43,7 @@ CNF1_LPC_EN | FDD_LPC_EN); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32;
diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c index 4f7ca3a..8d36f6b 100644 --- a/src/mainboard/hp/2570p/romstage.c +++ b/src/mainboard/hp/2570p/romstage.c @@ -24,10 +24,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 0, 1, 0 }, diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c index a696fae..5bf8789 100644 --- a/src/mainboard/hp/2760p/romstage.c +++ b/src/mainboard/hp/2760p/romstage.c @@ -23,10 +23,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 1, 1, 0 }, diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c index 77c355b..397810e 100644 --- a/src/mainboard/hp/8460p/romstage.c +++ b/src/mainboard/hp/8460p/romstage.c @@ -27,10 +27,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* USB0, eSATA */ { 1, 0, 0 }, /* USB charger */ diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c index 890e65b..513b375 100644 --- a/src/mainboard/hp/8470p/romstage.c +++ b/src/mainboard/hp/8470p/romstage.c @@ -26,10 +26,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 1, 1, 0 }, diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c index 49a5b1a..d3034fb 100644 --- a/src/mainboard/hp/8770w/romstage.c +++ b/src/mainboard/hp/8770w/romstage.c @@ -27,10 +27,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* Dock USB3.0 */ { 1, 1, 0 }, /* Conn */ diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c index 90cfcc9..3e726cf 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c @@ -31,10 +31,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, { 1, 0, -1 }, diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c index 3f174a1..969b666 100644 --- a/src/mainboard/hp/folio_9470m/romstage.c +++ b/src/mainboard/hp/folio_9470m/romstage.c @@ -25,10 +25,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* SSP1: dock */ { 1, 1, 0 }, /* SSP2: left, EHCI Debug */ diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c index 8a40578..844bb2f 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -28,7 +28,7 @@ { }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { RCBA32(BUC) = 0x00000000; } diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/romstage.c index bd0a377..2e0a508 100644 --- a/src/mainboard/hp/z220_sff_workstation/romstage.c +++ b/src/mainboard/hp/z220_sff_workstation/romstage.c @@ -31,10 +31,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 7f3a58d..1cd58b0 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -31,7 +31,7 @@ { }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Disable devices */ RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI; diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index e7959ef..16a16de 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -43,11 +43,6 @@ } }
-void mainboard_rcba_config(void) -{ - southbridge_configure_default_intmap(); -} - void mainboard_config_superio(void) { const u16 port = SIO_PORT; diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index f778f96..37713e1 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -43,7 +43,7 @@ COMA_LPC_EN | COMB_LPC_EN); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32;
diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index fc67e5a..37182f8 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -26,10 +26,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, { 1, 0, -1 }, diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 48d26c2..ee1d0ed 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -42,7 +42,7 @@ ec_mm_set_bit(0x3b, 4); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Disable devices. */ RCBA32(BUC) = 0x00000020; diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index e7851f3..7036ec4 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -54,10 +54,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - // OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: system port 4, OC0 */ diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 72cbcad..7b97ff7 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -54,10 +54,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 1, -1 }, /* P0 empty */ { 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */ diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index 3caa443..0cff5d2 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -53,10 +53,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - /* FIXME: used T530 values here */ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 34793d1..298673b 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -24,10 +24,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 75e331e..52898fa 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -56,10 +56,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0 left dual conn, OC 0 */ { 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */ diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index cb17a27..e0b0455 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -56,10 +56,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index 6f176c7..a1d3e88 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -24,10 +24,6 @@ { }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index eb2a5b1..f4d2a3c 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -68,10 +68,6 @@ return spd_file + spd_index * 256; }
-void mainboard_rcba_config(void) -{ -} - void mainboard_get_spd(spd_raw_data *spd, bool id_only) { uint8_t *memory; diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 8460208..7989fd6 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -32,10 +32,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 6f10135..3e9ea2c 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -29,10 +29,6 @@ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */ { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */ diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/romstage.c index 8f83c86..399d44b 100644 --- a/src/mainboard/msi/ms7707/romstage.c +++ b/src/mainboard/msi/ms7707/romstage.c @@ -28,10 +28,6 @@ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xa4, reg16); }
-void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { {1, 0, 0}, {1, 0, 0}, diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/romstage.c index a54a9ad..f168138 100644 --- a/src/mainboard/roda/rv11/romstage.c +++ b/src/mainboard/roda/rv11/romstage.c @@ -16,7 +16,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h>
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32;
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index d4b6dd8..ddcf2ad 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -51,7 +51,7 @@ #endif }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* * GFX INTA -> PIRQA (MSI) diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 77fd160..0665997 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -62,7 +62,7 @@ #endif }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* * GFX INTA -> PIRQA (MSI) diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index 7fcde77..3c9cc82 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -26,7 +26,7 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); }
-void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Disable devices. */ RCBA32(0x3414) = 0x00000020; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 92882b4..c76d2f4 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -34,6 +34,10 @@ { }
+__weak void mainboard_late_rcba_config(void) +{ +} + static void early_pch_reset_pmcon(void) { u8 reg8; @@ -100,7 +104,7 @@
southbridge_configure_default_intmap(); southbridge_rcba_config(); - mainboard_rcba_config(); + mainboard_late_rcba_config();
post_code(0x3d);
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index ac976c2..d4cd86e 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -72,7 +72,9 @@ void early_thermal_init(void); void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); -void mainboard_rcba_config(void); +/* Optional mainboard hook to do additional configuration + on the RCBA config space. It is called after the raminit. */ +void mainboard_late_rcba_config(void); void early_pch_init_native(void); void early_pch_init(void); void early_pch_init_native_dmi_pre(void);
-
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