Change in ...coreboot[master]: vendorcode/google/chromeos: Add CHROMEOS_SOC_DEBUG_CONSENT Kconfig
Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32337
Change subject: vendorcode/google/chromeos: Add CHROMEOS_SOC_DEBUG_CONSENT Kconfig ......................................................................
vendorcode/google/chromeos: Add CHROMEOS_SOC_DEBUG_CONSENT Kconfig
CHROMEOS_SOC_DEBUG_CONSENT config is generally to enable SOC debug capability. Ex: USB DBC debug capability on cnl.
Change-Id: I313d80d6c63fd37164c63f78e9e69d3cb4a5566b Signed-off-by: Kane Chen kane.chen@intel.com --- M src/vendorcode/google/chromeos/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32337/1
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 26ee31e..0ea5625 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -89,5 +89,9 @@ on normal boot as well as resume and coreboot is only involved in the resume piece w.r.t. the platform hierarchy.
+config CHROMEOS_SOC_DEBUG_CONSENT + bool "Enable SOC debug capability" + default n + endif # CHROMEOS endmenu
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32337 )
Change subject: vendorcode/google/chromeos: Add CHROMEOS_SOC_DEBUG_CONSENT Kconfig ......................................................................
Patch Set 1:
Why is it Chromium OS specific?
Hello build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32337
to look at the new patch set (#2).
Change subject: vendorcode/google/chromeos: Add CHROMEOS_SOC_DEBUG_CONSENT Kconfig ......................................................................
vendorcode/google/chromeos: Add CHROMEOS_SOC_DEBUG_CONSENT Kconfig
CHROMEOS_SOC_DEBUG_CONSENT config is generally to enable SOC debug capability. Ex: USB DBC debug capability on cnl.
Change-Id: I313d80d6c63fd37164c63f78e9e69d3cb4a5566b Signed-off-by: Kane Chen kane.chen@intel.com --- M src/vendorcode/google/chromeos/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32337/2
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32337 )
Change subject: vendorcode/google/chromeos: Add CHROMEOS_SOC_DEBUG_CONSENT Kconfig ......................................................................
Patch Set 2:
Patch Set 1:
Why is it Chromium OS specific?
it's not Chromium OS specific. Other OS can directly control DEBUG_CONSENT_CANNONLAKE.
it's main switch for chrome OS developers to control soc debug capability like DEBUG_CONSENT_CANNONLAKE config.
Going forward, there might be some other new settings for other chipset to enable debug capability and this main switch can still be used
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32337 )
Change subject: vendorcode/google/chromeos: Add CHROMEOS_SOC_DEBUG_CONSENT Kconfig ......................................................................
Patch Set 2:
This sounds like something that probably belons in soc/intel/common instead (although I don't fully understand the purpose yet tbh).
Note that if you want to enable something specifically for Chrome OS developer builds (e.g. builds that have serial console enabled), the correct place to set it is in the fwserial.<board> config file in the coreboot ebuild in the Chromium source tree. We probably wouldn't want debug features to be enabled on production Chromebooks either?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32337 )
Change subject: vendorcode/google/chromeos: Add CHROMEOS_SOC_DEBUG_CONSENT Kconfig ......................................................................
Patch Set 2:
Patch Set 2:
This sounds like something that probably belons in soc/intel/common instead (although I don't fully understand the purpose yet tbh).
Yes, this is something which is very Intel specific at this point and it should be put into soc/intel/common/Kconfig
To provide some background: Kane is working on providing an easy way to generate coreboot builds that allow Intel USB3 DBC debugging on Chrome OS. So, by default BIOS built for Chrome OS will not have this debug feature enabled. However, a use flag can be used something like USE="intel-dbc" to generate debug enabled image as required by the partners.
Note that if you want to enable something specifically for Chrome OS developer builds (e.g. builds that have serial console enabled), the correct place to set it is in the fwserial.<board> config file in the coreboot ebuild in the Chromium source tree. We probably wouldn't want debug features to be enabled on production Chromebooks either?
This feature will not be enabled on production or serial console enabled binaries by default. It is mostly to provide an easy way for partners to build BIOS images without having to make changes in code.
Kane, I think the right way to do this would be:
1. Add this Kconfig to soc/intel/common - SOC_INTEL_DEBUG_CONSENT 2. In specific SoCs(e.g. cannonlake), you can set DEBUG_CONSENT_CANNONLAKE to DBC if CHROMEOS and SOC_INTEL_DEBUG_CONSENT are selected. Then you don't have to make changes to mainboard as well.
Hello build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32337
to look at the new patch set (#3).
Change subject: soc/intel/common: SOC_INTEL_DEBUG_CONSENT to control debug interface ......................................................................
soc/intel/common: SOC_INTEL_DEBUG_CONSENT to control debug interface
SOC_INTEL_DEBUG_CONSENT config is generally to enable SOC debug interface. Ex: USB DBC, DCI debug interface on cnl, whl, cml.
Change-Id: I313d80d6c63fd37164c63f78e9e69d3cb4a5566b Signed-off-by: Kane Chen kane.chen@intel.com --- M src/soc/intel/common/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32337/3
Hello Patrick Rudolph, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32337
to look at the new patch set (#4).
Change subject: soc/intel/common: SOC_INTEL_DEBUG_CONSENT to control debug interface ......................................................................
soc/intel/common: SOC_INTEL_DEBUG_CONSENT to control debug interface
SOC_INTEL_DEBUG_CONSENT config is generally to enable SOC debug interface. Ex: USB DBC, DCI debug interface on cnl, whl, cml.
Change-Id: I313d80d6c63fd37164c63f78e9e69d3cb4a5566b Signed-off-by: Kane Chen kane.chen@intel.com --- M src/soc/intel/common/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32337/4
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32337 )
Change subject: soc/intel/common: SOC_INTEL_DEBUG_CONSENT to control debug interface ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/32337/4/src/soc/intel/common/Kconfig File src/soc/intel/common/Kconfig:
https://review.coreboot.org/#/c/32337/4/src/soc/intel/common/Kconfig@75 PS4, Line 75: will enable SOC debug interface to enable default debug interface of SoC?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32337 )
Change subject: soc/intel/common: SOC_INTEL_DEBUG_CONSENT to control debug interface ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/32337/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32337/4//COMMIT_MSG@9 PS4, Line 9: SOC debug : interface. default debug interface of SoC.
Hello Patrick Rudolph, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32337
to look at the new patch set (#5).
Change subject: soc/intel/common: SOC_INTEL_DEBUG_CONSENT to control debug interface ......................................................................
soc/intel/common: SOC_INTEL_DEBUG_CONSENT to control debug interface
SOC_INTEL_DEBUG_CONSENT config is generally to enable default debug interface of SoC.
Ex: USB DBC, DCI debug interface on cnl, whl, cml.
Change-Id: I313d80d6c63fd37164c63f78e9e69d3cb4a5566b Signed-off-by: Kane Chen kane.chen@intel.com --- M src/soc/intel/common/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32337/5
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32337 )
Change subject: soc/intel/common: SOC_INTEL_DEBUG_CONSENT to control debug interface ......................................................................
Patch Set 5: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32337 )
Change subject: soc/intel/common: SOC_INTEL_DEBUG_CONSENT to control debug interface ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/32337/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32337/5//COMMIT_MSG@7 PS5, Line 7: soc/intel/common: SOC_INTEL_DEBUG_CONSENT to control debug interface Please make it a statement by adding a verb.
Add …
Hello Patrick Rudolph, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32337
to look at the new patch set (#6).
Change subject: soc/intel/common: Add SOC_INTEL_DEBUG_CONSENT to control debug interface ......................................................................
soc/intel/common: Add SOC_INTEL_DEBUG_CONSENT to control debug interface
SOC_INTEL_DEBUG_CONSENT config is generally to enable default debug interface of SoC.
Ex: USB DBC, DCI debug interface on cnl, whl, cml.
Change-Id: I313d80d6c63fd37164c63f78e9e69d3cb4a5566b Signed-off-by: Kane Chen kane.chen@intel.com --- M src/soc/intel/common/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32337/6
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32337 )
Change subject: soc/intel/common: Add SOC_INTEL_DEBUG_CONSENT to control debug interface ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/32337/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32337/5//COMMIT_MSG@7 PS5, Line 7: soc/intel/common: SOC_INTEL_DEBUG_CONSENT to control debug interface
Please make it a statement by adding a verb. […]
Done
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32337 )
Change subject: soc/intel/common: Add SOC_INTEL_DEBUG_CONSENT to control debug interface ......................................................................
soc/intel/common: Add SOC_INTEL_DEBUG_CONSENT to control debug interface
SOC_INTEL_DEBUG_CONSENT config is generally to enable default debug interface of SoC.
Ex: USB DBC, DCI debug interface on cnl, whl, cml.
Change-Id: I313d80d6c63fd37164c63f78e9e69d3cb4a5566b Signed-off-by: Kane Chen kane.chen@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32337 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index b5caf40..318cc25 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -68,4 +68,11 @@ acpi_get_gpe() is used to provide interrupt status to TPM layer. This option specifies the GPE number.
+config SOC_INTEL_DEBUG_CONSENT + bool "Enable SOC debug interface" + default n + help + Set this option to enable default debug interface of SoC such as DBC + or DCI. + endif # SOC_INTEL_COMMON
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Furquan Shaikh (Code Review) -
Julius Werner (Code Review)
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Kane Chen (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)