HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40666 )
Change subject: src: Remove unused 'include <cpu/x86/cache.h> ......................................................................
src: Remove unused 'include <cpu/x86/cache.h>
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/mtrr/earlymtrr.c M src/cpu/x86/smm/smihandler.c M src/cpu/x86/smm/smm_module_loader.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/gma/intel_ddi.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/raminit.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/quark/romstage/fsp_params.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/tigerlake/smmrelocate.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/smi.c 35 files changed, 0 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/40666/1
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index aab830f..82c28bf 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -13,7 +13,6 @@ #include <cpu/intel/smm_reloc.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <cpu/x86/smm.h> #include <delay.h> diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 9ac9913..cf3a873 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 018a478..d52bcbc 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -9,7 +9,6 @@ #include <device/device.h> #include <device/pci.h> #include <commonlib/helpers.h> -#include <cpu/x86/cache.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index baf87c8..46ccc3d 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */
-#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
.global bootblock_pre_c_entry diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 4d14a8d..5df24fa 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -2,7 +2,6 @@ /* This file is part of the coreboot project. */
#include <cpu/cpu.h> -#include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h>
diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index bfbdfd2..2e929d1 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -3,7 +3,6 @@
#include <arch/io.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <cpu/x86/smi_deprecated.h> #include <cpu/amd/amd64_save_state.h> diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 7c23ef8..bdcf283 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -4,7 +4,6 @@ #include <string.h> #include <rmodule.h> #include <cpu/x86/smm.h> -#include <cpu/x86/cache.h> #include <commonlib/helpers.h> #include <console/console.h> #include <security/intel/stm/SmmStm.h> diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index 735f257..7055233 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -7,7 +7,6 @@ #include <commonlib/helpers.h> #include <cpu/amd/mtrr.h> #include <cpu/cpu.h> -#include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index d52b293..3a8fe50 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -35,7 +35,6 @@ #include <device/pci.h> #include <ec/google/chromeec/ec.h> #include <cpu/x86/tsc.h> -#include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <edid.h> diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 8ed5007..fd88193 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -21,7 +21,6 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <assert.h> #include <spd.h> diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 18e1faa..aea699e 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -18,7 +18,6 @@ #include <device/pci_ops.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <delay.h> #include <lib.h> #include "pineview.h" diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index f1dc881..797bc5a 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -17,7 +17,6 @@ #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <arch/cpu.h> #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index cd21fde..73f5614 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -18,7 +18,6 @@ #include <console/console.h> #include "chip.h" #include <cpu/cpu.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index d2a8e57..0672803 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -8,7 +8,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index bb77742..e3c1f1b 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -8,7 +8,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 218232f..9e68410 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -4,7 +4,6 @@ #include <stdint.h> #include <arch/bootblock.h> #include <arch/io.h> -#include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <halt.h> diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index b630c0a..35df1b5 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -14,7 +14,6 @@ #include <cpu/intel/smm_reloc.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <cpu/x86/smm.h> #include <delay.h> diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 6860f6f..95d45ea 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -5,7 +5,6 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> -#include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> #include <soc/iomap.h> diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index f5f83f6..4adc281 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 7828097..ce42767 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 68d3e32..26c938b 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -15,7 +15,6 @@
#include <device/pci_def.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h>
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 036a47a..ab90123 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -15,7 +15,6 @@
#include <console/console.h> #include <cpu/cpu.h> -#include <cpu/x86/cache.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 365424e..874ba32 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c index be3abdf..78b0375 100644 --- a/src/soc/intel/jasperlake/smmrelocate.c +++ b/src/soc/intel/jasperlake/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c index ed362ea..d555b34 100644 --- a/src/soc/intel/quark/romstage/fsp_params.c +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -6,7 +6,6 @@ #include <console/console.h> #include <cbmem.h> #include "../chip.h" -#include <cpu/x86/cache.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index ad26c57..5f2938c 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -14,7 +14,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 3d34616..7db79a6 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index be3abdf..78b0375 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 78ac08b..b2b635f 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -5,7 +5,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 5de5d41..a471eef 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -3,7 +3,6 @@
#include <types.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <southbridge/intel/common/pmbase.h> diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 8f9544b..f303ef4 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -6,7 +6,6 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> -#include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> #include <southbridge/intel/common/pmbase.h> diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 8a19848..9282021 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -3,7 +3,6 @@
#include <types.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <southbridge/intel/common/pmutil.h> diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 5c1edbc..de9148e 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -3,7 +3,6 @@
#include <types.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <southbridge/intel/common/pmutil.h> diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index a7c1e5f..05cd20f 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -5,7 +5,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 05b5bb5..4c8ccfa 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -7,7 +7,6 @@ #include <console/console.h> #include <arch/io.h> #include <cpu/intel/smm_reloc.h> -#include <cpu/x86/cache.h> #include <cpu/x86/smm.h>
#include "pch.h"
Hello build bot (Jenkins), Damien Zammit, David Guckian, Vanessa Eusebio, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40666
to look at the new patch set (#2).
Change subject: src: Remove unused 'include <cpu/x86/cache.h>' ......................................................................
src: Remove unused 'include <cpu/x86/cache.h>'
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/mtrr/earlymtrr.c M src/cpu/x86/smm/smihandler.c M src/cpu/x86/smm/smm_module_loader.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/gma/intel_ddi.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/raminit.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/quark/romstage/fsp_params.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/tigerlake/smmrelocate.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/smi.c 35 files changed, 0 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/40666/2
Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40666 )
Change subject: src: Remove unused 'include <cpu/x86/cache.h>' ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40666 )
Change subject: src: Remove unused 'include <cpu/x86/cache.h>' ......................................................................
Patch Set 2: Code-Review+1
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40666 )
Change subject: src: Remove unused 'include <cpu/x86/cache.h>' ......................................................................
src: Remove unused 'include <cpu/x86/cache.h>'
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666 Reviewed-by: Stefan Reinauer stefan.reinauer@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/mtrr/earlymtrr.c M src/cpu/x86/smm/smihandler.c M src/cpu/x86/smm/smm_module_loader.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/gma/intel_ddi.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/raminit.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/quark/romstage/fsp_params.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/tigerlake/smmrelocate.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/smi.c 35 files changed, 0 insertions(+), 35 deletions(-)
Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index aab830f..82c28bf 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -13,7 +13,6 @@ #include <cpu/intel/smm_reloc.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <cpu/x86/smm.h> #include <delay.h> diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 9ac9913..cf3a873 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 018a478..d52bcbc 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -9,7 +9,6 @@ #include <device/device.h> #include <device/pci.h> #include <commonlib/helpers.h> -#include <cpu/x86/cache.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index baf87c8..46ccc3d 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */
-#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
.global bootblock_pre_c_entry diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index e400359..e8608fd 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -2,7 +2,6 @@ /* This file is part of the coreboot project. */
#include <cpu/cpu.h> -#include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h>
diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index bfbdfd2..2e929d1 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -3,7 +3,6 @@
#include <arch/io.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <cpu/x86/smi_deprecated.h> #include <cpu/amd/amd64_save_state.h> diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 7c23ef8..bdcf283 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -4,7 +4,6 @@ #include <string.h> #include <rmodule.h> #include <cpu/x86/smm.h> -#include <cpu/x86/cache.h> #include <commonlib/helpers.h> #include <console/console.h> #include <security/intel/stm/SmmStm.h> diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index 735f257..7055233 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -7,7 +7,6 @@ #include <commonlib/helpers.h> #include <cpu/amd/mtrr.h> #include <cpu/cpu.h> -#include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index d52b293..3a8fe50 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -35,7 +35,6 @@ #include <device/pci.h> #include <ec/google/chromeec/ec.h> #include <cpu/x86/tsc.h> -#include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <edid.h> diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 8ed5007..fd88193 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -21,7 +21,6 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <assert.h> #include <spd.h> diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 18e1faa..aea699e 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -18,7 +18,6 @@ #include <device/pci_ops.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <delay.h> #include <lib.h> #include "pineview.h" diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index f1dc881..797bc5a 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -17,7 +17,6 @@ #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <arch/cpu.h> #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index cd21fde..73f5614 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -18,7 +18,6 @@ #include <console/console.h> #include "chip.h" #include <cpu/cpu.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index d2a8e57..0672803 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -8,7 +8,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index bb77742..e3c1f1b 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -8,7 +8,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 218232f..9e68410 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -4,7 +4,6 @@ #include <stdint.h> #include <arch/bootblock.h> #include <arch/io.h> -#include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <halt.h> diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index b630c0a..35df1b5 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -14,7 +14,6 @@ #include <cpu/intel/smm_reloc.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <cpu/x86/smm.h> #include <delay.h> diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 6860f6f..95d45ea 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -5,7 +5,6 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> -#include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> #include <soc/iomap.h> diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index f5f83f6..4adc281 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 7828097..ce42767 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 68d3e32..26c938b 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -15,7 +15,6 @@
#include <device/pci_def.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h>
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 036a47a..ab90123 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -15,7 +15,6 @@
#include <console/console.h> #include <cpu/cpu.h> -#include <cpu/x86/cache.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 365424e..874ba32 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c index be3abdf..78b0375 100644 --- a/src/soc/intel/jasperlake/smmrelocate.c +++ b/src/soc/intel/jasperlake/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c index ed362ea..d555b34 100644 --- a/src/soc/intel/quark/romstage/fsp_params.c +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -6,7 +6,6 @@ #include <console/console.h> #include <cbmem.h> #include "../chip.h" -#include <cpu/x86/cache.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index ad26c57..5f2938c 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -14,7 +14,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 3d34616..7db79a6 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index be3abdf..78b0375 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 78ac08b..b2b635f 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -5,7 +5,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 5de5d41..a471eef 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -3,7 +3,6 @@
#include <types.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <southbridge/intel/common/pmbase.h> diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 8f9544b..f303ef4 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -6,7 +6,6 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> -#include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> #include <southbridge/intel/common/pmbase.h> diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 8a19848..9282021 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -3,7 +3,6 @@
#include <types.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <southbridge/intel/common/pmutil.h> diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 5c1edbc..de9148e 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -3,7 +3,6 @@
#include <types.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <southbridge/intel/common/pmutil.h> diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index a7c1e5f..05cd20f 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -5,7 +5,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 05b5bb5..4c8ccfa 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -7,7 +7,6 @@ #include <console/console.h> #include <arch/io.h> #include <cpu/intel/smm_reloc.h> -#include <cpu/x86/cache.h> #include <cpu/x86/smm.h>
#include "pch.h"
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40666 )
Change subject: src: Remove unused 'include <cpu/x86/cache.h>' ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2982 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2981 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2980 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/2979
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
HAOUAS Elyes (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
-
Stefan Reinauer (Code Review)