Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68191 )
Change subject: vc/amd/fsp: Make common directory ......................................................................
vc/amd/fsp: Make common directory
The common directory is for files that shouldn't change, or shouldn't change much between platforms.
These will be removed from other directories and used in upcoming commits.
Signed-off-by: Martin Roth martin.roth@amd.corp-partner.google.com Change-Id: I37ed98a67b066598fdebcc5b034e64dc639fda7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68191 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Fred Reitberger reitbergerfred@gmail.com Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com --- A src/vendorcode/amd/fsp/common/FspGuids.h A src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S A src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_header.inc A src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S A src/vendorcode/amd/fsp/common/ccx_cppc_data.h A src/vendorcode/amd/fsp/common/dmi_info.h A src/vendorcode/amd/fsp/common/fsp_h_c99.h A src/vendorcode/amd/fsp/common/include/bl_uapp/bl_errorcodes_public.h 8 files changed, 576 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve
diff --git a/src/vendorcode/amd/fsp/common/FspGuids.h b/src/vendorcode/amd/fsp/common/FspGuids.h new file mode 100644 index 0000000..1bef794 --- /dev/null +++ b/src/vendorcode/amd/fsp/common/FspGuids.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __FSP_GUIDS__ +#define __FSP_GUIDS__ + +#include <uuid.h> + +#define AMD_FSP_TSEG_HOB_GUID \ + GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \ + 0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c) + +#define AMD_FSP_ACPI_ALIB_HOB_GUID \ + GUID_INIT(0x42494c41, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID \ + GUID_INIT(0X6D5CD69D, 0XFB24, 0X4461, \ + 0XAA, 0X32, 0X8E, 0XE1, 0XB3, 0X3, 0X31, 0X9C ) + +#define AMD_FSP_CCX_CPPC_DATA_HOB_GUID \ + GUID_INIT(0x3060C5EC, 0x7399, 0x432D, \ + 0xBC, 0x97, 0xBF, 0x95, 0xE4, 0x3D, 0x53, 0x0C ) + +#endif /* __FSP_GUIDS__ */ diff --git a/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S b/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S new file mode 100644 index 0000000..40ea411 --- /dev/null +++ b/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S @@ -0,0 +1,44 @@ +/***************************************************************************** + * + * Copyright (c) 2019, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +.arm +.global LastBytes +.section PSP_FOOTER_DATA, "ad", %note +.balign 64 + +// Note: this is used for determining the size of the binary. It is 64 byte aligned and 64 byte +// in size so that the binary size is multiple of 64 bytes. +// +LastBytes: + .byte 0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99 + .byte 0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99 + .byte 0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99 + .byte 0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99 + +.end diff --git a/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_header.inc b/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_header.inc new file mode 100644 index 0000000..bb90f67 --- /dev/null +++ b/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_header.inc @@ -0,0 +1,64 @@ +/***************************************************************************** + * + * Copyright (c) 2019, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +.global LastBytes + +#define BL_UAPP_START_ADDRESS 0x00036000 +#define SIZE_OF_THIS_HEADER 256 +#define SIZE_OF_PSP_END 64 +#define IMAGE_SIZE LastBytes + SIZE_OF_PSP_END - BL_UAPP_START_ADDRESS - SIZE_OF_THIS_HEADER + +#define IMAGE_VERSION 0x01,0x00,0x00,0x00 +#define FW_TYPE 0x52 + + + // 256 byte binary header + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 // nonce + .byte 0x00,0x00,0x00,0x00 // header version + .word IMAGE_SIZE + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x49,0x01,0x00,0x00,0x00,0x00,0x00,0x00 + .byte IMAGE_VERSION + .byte 0x00,0x00,0x00,0x00 // APU Family ID + .byte 0x00,0x01,0x00,0x00 // Load Address + .byte 0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte FW_TYPE + .byte 0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 diff --git a/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S b/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S new file mode 100644 index 0000000..f5f1e18e --- /dev/null +++ b/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S @@ -0,0 +1,71 @@ +/***************************************************************************** + * + * Copyright (c) 2019, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#include <arch/asm.h> +#include <bl_uapp/bl_errorcodes_public.h> + + .global Main + .global _psp_vs_start + + .global PSP_VERSTAGE_STACK_END + +.arm +.text +.section "PSP_HEADER_DATA", "aw", %note + +//============================================================================== +// First 256 bytes of the binary image contain the header. +// Executable code starts from offset 0x100. +//============================================================================== +#include "bl_uapp_header.inc" + +//============================================================================== +// This is entry point to the binary which is called by main Boot Loader. +//============================================================================== + +ENTRY(_psp_vs_start) + + ldr sp, =PSP_VERSTAGE_STACK_END // stack pointer + + // Return value contains Virtual Address of mapped stack + // + ldr lr, =ShouldNotBeReached // return address + + ldr r2, =Main // pass control to verstage main function + blx r2 + +// This point should not be reached. The Main() function should return +// to main BL using Svc_Exit(). +// +ShouldNotBeReached: + mov r0, #BL_ERR_GENERIC // Returned from Main + svc #0x0 // SVC_EXIT + +ENDPROC(_psp_vs_start) +.end diff --git a/src/vendorcode/amd/fsp/common/ccx_cppc_data.h b/src/vendorcode/amd/fsp/common/ccx_cppc_data.h new file mode 100644 index 0000000..ac88776 --- /dev/null +++ b/src/vendorcode/amd/fsp/common/ccx_cppc_data.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef COMMOM_FSP_CCX_CPPC_DATA_H +#define COMMON_FSP_CCX_CPPC_DATA_H + +#include <types.h> + +#define FSP_CCX_CPPC_DATA_VERSION 1 + +struct fsp_ccx_cppc_data { + uint8_t version; + uint8_t unused[3]; + uint32_t ccx_cppc_min_speed; + uint32_t ccx_cppc_nom_speed; +} __packed; + +#endif /* COMMON_FSP_CCX_CPPC_DATA_H */ diff --git a/src/vendorcode/amd/fsp/common/dmi_info.h b/src/vendorcode/amd/fsp/common/dmi_info.h new file mode 100644 index 0000000..bd9ac5f --- /dev/null +++ b/src/vendorcode/amd/fsp/common/dmi_info.h @@ -0,0 +1,241 @@ + /***************************************************************************** + * + * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/** + * This code was copied from src/vendorcode/amd/pi/00670F00/AGESA.h + */ + +#define AMD_FSP_DMI_HOB_GUID {0x4118FC0E, 0x353D, 0x4726, { 0x97, 0xC0, 0x53, 0xCD, 0x92, 0xB6, 0x49, 0x25}} + +// Our ACPI HOB max payload, accounting for the size of the HOB header as well as the information structure +#define HOB_MAX_SIZE 0xFFF8 +#define HOB_GUID_EXTENSION_SIZE (HOB_MAX_SIZE - sizeof (EFI_HOB_GUID_TYPE)) + +#define MAX_SOCKETS_SUPPORTED 2 ///< Max number of sockets in system +#define MAX_CHANNELS_PER_SOCKET 8 ///< Max Channels per sockets +#define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform) + +/// DMI Type 16 offset 04h - Location +typedef enum { + OtherLocation = 0x01, ///< Assign 01 to Other + UnknownLocation, ///< Assign 02 to Unknown + SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard + IsaAddonCard, ///< Assign 04 to ISA add-on card + EisaAddonCard, ///< Assign 05 to EISA add-on card + PciAddonCard, ///< Assign 06 to PCI add-on card + McaAddonCard, ///< Assign 07 to MCA add-on card + PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card + ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card + NuBus, ///< Assign 0A to NuBus + Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card + Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card + Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card + Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card +} DMI_T16_LOCATION; + +/// DMI Type 16 offset 05h - Memory Error Correction +typedef enum { + OtherUse = 0x01, ///< Assign 01 to Other + UnknownUse, ///< Assign 02 to Unknown + SystemMemory, ///< Assign 03 to system memory + VideoMemory, ///< Assign 04 to video memory + FlashMemory, ///< Assign 05 to flash memory + NonvolatileRam, ///< Assign 06 to non-volatile RAM + CacheMemory ///< Assign 07 to cache memory +} DMI_T16_USE; + +/// DMI Type 16 offset 07h - Maximum Capacity +typedef enum { + Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other + Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown + Dmi16NoneErrCorrection, ///< Assign 03 to None + Dmi16Parity, ///< Assign 04 to parity + Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC + Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC + Dmi16Crc ///< Assign 07 to CRC +} DMI_T16_ERROR_CORRECTION; + +/// DMI Type 16 - Physical Memory Array +typedef struct { + OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array, + ///< whether on the system board or an add-in board. + OUT DMI_T16_USE Use; ///< Identifies the function for which the array + ///< is used. + OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or + ///< detection method supported by this memory array. + OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available + ///< for memory devices in this array. +} TYPE16_DMI_INFO; + +/// DMI Type 17 offset 0Eh - Form Factor +typedef enum { + OtherFormFactor = 0x01, ///< Assign 01 to Other + UnknowFormFactor, ///< Assign 02 to Unknown + SimmFormFactor, ///< Assign 03 to SIMM + SipFormFactor, ///< Assign 04 to SIP + ChipFormFactor, ///< Assign 05 to Chip + DipFormFactor, ///< Assign 06 to DIP + ZipFormFactor, ///< Assign 07 to ZIP + ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card + DimmFormFactorFormFactor, ///< Assign 09 to DIMM + TsopFormFactor, ///< Assign 10 to TSOP + RowOfChipsFormFactor, ///< Assign 11 to Row of chips + RimmFormFactor, ///< Assign 12 to RIMM + SodimmFormFactor, ///< Assign 13 to SODIMM + SrimmFormFactor, ///< Assign 14 to SRIMM + FbDimmFormFactor ///< Assign 15 to FB-DIMM +} DMI_T17_FORM_FACTOR; + +/// DMI Type 17 offset 12h - Memory Type +typedef enum { + OtherMemType = 0x01, ///< Assign 01 to Other + UnknownMemType, ///< Assign 02 to Unknown + DramMemType, ///< Assign 03 to DRAM + EdramMemType, ///< Assign 04 to EDRAM + VramMemType, ///< Assign 05 to VRAM + SramMemType, ///< Assign 06 to SRAM + RamMemType, ///< Assign 07 to RAM + RomMemType, ///< Assign 08 to ROM + FlashMemType, ///< Assign 09 to Flash + EepromMemType, ///< Assign 10 to EEPROM + FepromMemType, ///< Assign 11 to FEPROM + EpromMemType, ///< Assign 12 to EPROM + CdramMemType, ///< Assign 13 to CDRAM + ThreeDramMemType, ///< Assign 14 to 3DRAM + SdramMemType, ///< Assign 15 to SDRAM + SgramMemType, ///< Assign 16 to SGRAM + RdramMemType, ///< Assign 17 to RDRAM + DdrMemType, ///< Assign 18 to DDR + Ddr2MemType, ///< Assign 19 to DDR2 + Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM + Ddr3MemType = 0x18, ///< Assign 24 to DDR3 + Fbd2MemType, ///< Assign 25 to FBD2 + Ddr4MemType, ///< Assign 26 to DDR4 + LpDdrMemType, ///< Assign 27 to LPDDR + LpDdr2MemType, ///< Assign 28 to LPDDR2 + LpDdr3MemType, ///< Assign 29 to LPDDR3 + LpDdr4MemType, ///< Assign 30 to LPDDR4 + Ddr5MemType = 0x22, ///< Assign 34 to DDR5 + LpDdr5MemType, ///< Assign 35 to LPDDR5 + LpDdr5xMemType, ///< Assign 36 to LPDDR5X +} DMI_T17_MEMORY_TYPE; + +/// DMI Type 17 offset 13h - Type Detail +typedef struct { + OUT UINT16 Reserved1:1; ///< Reserved + OUT UINT16 Other:1; ///< Other + OUT UINT16 Unknown:1; ///< Unknown + OUT UINT16 FastPaged:1; ///< Fast-Paged + OUT UINT16 StaticColumn:1; ///< Static column + OUT UINT16 PseudoStatic:1; ///< Pseudo-static + OUT UINT16 Rambus:1; ///< RAMBUS + OUT UINT16 Synchronous:1; ///< Synchronous + OUT UINT16 Cmos:1; ///< CMOS + OUT UINT16 Edo:1; ///< EDO + OUT UINT16 WindowDram:1; ///< Window DRAM + OUT UINT16 CacheDram:1; ///< Cache Dram + OUT UINT16 NonVolatile:1; ///< Non-volatile + OUT UINT16 Registered:1; ///< Registered (Buffered) + OUT UINT16 Unbuffered:1; ///< Unbuffered (Unregistered) + OUT UINT16 LRDIMM:1; ///< LRDIMM +} DMI_T17_TYPE_DETAIL; + +/// DMI Type 17 offset 28h - Memory Technology +typedef enum { + OtherType = 0x01, ///< Assign 01 to Other + UnknownType = 0x02, ///< Assign 02 to Unknown + DramType = 0x03, ///< Assign 03 to DRAM + NvDimmNType = 0x04, ///< Assign 04 to NVDIMM-N + NvDimmFType = 0x05, ///< Assign 05 to NVDIMM-F + NvDimmPType = 0x06, ///< Assign 06 to NVDIMM-P + IntelPersistentMemoryType = 0x07, ///< Assign 07 to Intel persistent memory +} DMI_T17_MEMORY_TECHNOLOGY; + +/// DMI Type 17 offset 29h - Memory Operating Mode Capability +typedef struct { + OUT UINT16 Reserved1:1; ///< Reserved, set to 0 + OUT UINT16 Other:1; ///< Other + OUT UINT16 Unknown:1; ///< Unknown + OUT UINT16 VolatileMemory:1; ///< Volatile memory + OUT UINT16 ByteAccessiblePersistentMemory:1; ///< Byte-accessible persistent memory + OUT UINT16 BlockAccessiblePersistentMemory:1; ///< Block-accessible persistent memory + OUT UINT16 Reserved2:10; ///< Reserved, set to 0 +} DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY; + +typedef union { + DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY AsBitmap; + UINT16 AsUint16; +} DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY_VAR; + +/// DMI Type 17 - Memory Device +typedef struct { + OUT UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure + OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. + OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. + OUT UINT16 MemorySize; ///< The size of the memory device. + OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. + OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of + ///< Memory Devices that must be populated with all devices of + ///< the same type and size, and the set to which this device belongs. + OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. + OUT CHAR8 BankLocator[13]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. + OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device. + OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type + OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). + OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. + OUT CHAR8 SerialNumber[9]; ///< Serial Number. + OUT CHAR8 PartNumber[21]; ///< Part Number. + OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. + OUT UINT32 ExtSize; ///< Extended Size. + OUT UINT16 ConfigSpeed; ///< Configured memory clock speed + OUT UINT16 MinimumVoltage; ///< Minimum operating voltage for this device, in millivolts + OUT UINT16 MaximumVoltage; ///< Maximum operating voltage for this device, in millivolts + OUT UINT16 ConfiguredVoltage; ///< Configured voltage for this device, in millivolts + // SMBIOS 3.2 + OUT UINT8 MemoryTechnology; ///< Memory technology type for this memory device + OUT DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY_VAR MemoryOperatingModeCapability; ///< The operating modes supported by this memory device + OUT CHAR8 FirmwareVersion[10]; ///< String number for the firmware version of this memory device + OUT UINT16 ModuleManufacturerId; ///< The two-byte module manufacturer ID found in the SPD of this memory device; LSB first. + OUT UINT16 ModuleProductId; ///< The two-byte module product ID found in the SPD of this memory device; LSB first + OUT UINT16 MemorySubsystemControllerManufacturerId; //< The two-byte memory subsystem controller manufacturer ID found in the SPD of this memory device; LSB first + OUT UINT16 MemorySubsystemControllerProductId; //< The two-byte memory subsystem controller product ID found in the SPD of this memory device; LSB first + OUT UINT64 NonvolatileSize; ///< Size of the Non-volatile portion of the memory device in Bytes, if any. + OUT UINT64 VolatileSize; ///< Size of the Volatile portion of the memory device in Bytes, if any. + OUT UINT64 CacheSize; ///< Size of the Cache portion of the memory device in Bytes, if any. + OUT UINT64 LogicalSize; ///< Size of the Logical memory device in Bytes. + // SMBIOS 3.3 + OUT UINT32 ExtendedSpeed; ///< Extended Speed + OUT UINT32 ExtendedConfiguredMemorySpeed; ///< Extended Configured memory speed +} __packed TYPE17_DMI_INFO; + +/// Collection of pointers to the DMI records +typedef struct { + OUT TYPE16_DMI_INFO T16; ///< Type 16 struc + OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc +} DMI_INFO; diff --git a/src/vendorcode/amd/fsp/common/fsp_h_c99.h b/src/vendorcode/amd/fsp/common/fsp_h_c99.h new file mode 100644 index 0000000..1a295f5 --- /dev/null +++ b/src/vendorcode/amd/fsp/common/fsp_h_c99.h @@ -0,0 +1,58 @@ +/** @file + * + * C99 common FSP definitions from + * Intel Firmware Support Package External Architecture Specification v2.0 + * + * These definitions come in a format that is usable outside an EFI environment. + **/ +#ifndef FSP_H_C99_H +#define FSP_H_C99_H + +#include <stdint.h> + +enum { + FSP_STATUS_RESET_REQUIRED_COLD = 0x40000001, + FSP_STATUS_RESET_REQUIRED_WARM = 0x40000002, + FSP_STATUS_RESET_REQUIRED_3 = 0x40000003, + FSP_STATUS_RESET_REQUIRED_4 = 0x40000004, + FSP_STATUS_RESET_REQUIRED_5 = 0x40000005, + FSP_STATUS_RESET_REQUIRED_6 = 0x40000006, + FSP_STATUS_RESET_REQUIRED_7 = 0x40000007, + FSP_STATUS_RESET_REQUIRED_8 = 0x40000008, +}; + +typedef enum { + EnumInitPhaseAfterPciEnumeration = 0x20, + EnumInitPhaseReadyToBoot = 0x40, + EnumInitPhaseEndOfFirmware = 0xF0 +} FSP_INIT_PHASE; + +typedef struct __packed { + uint64_t Signature; + uint8_t Revision; + uint8_t Reserved[23]; +} FSP_UPD_HEADER; + +_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed"); + + +#if CONFIG(PLATFORM_USES_FSP2_X86_32) +typedef struct __packed { + uint8_t Revision; + uint8_t Reserved[3]; + /* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */ + uint32_t NvsBufferPtr; + /* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */ + uint32_t StackBase; + uint32_t StackSize; + uint32_t BootLoaderTolumSize; + uint32_t BootMode; + uint8_t Reserved1[8]; +} FSPM_ARCH_UPD; + +_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed"); +#else +#error You need to implement this struct for x86_64 FSP +#endif + +#endif /* FSP_H_C99_H */ diff --git a/src/vendorcode/amd/fsp/common/include/bl_uapp/bl_errorcodes_public.h b/src/vendorcode/amd/fsp/common/include/bl_uapp/bl_errorcodes_public.h new file mode 100644 index 0000000..4fa9a33 --- /dev/null +++ b/src/vendorcode/amd/fsp/common/include/bl_uapp/bl_errorcodes_public.h @@ -0,0 +1,37 @@ +/***************************************************************************** + * + * Copyright (c) 2020, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +#ifndef BL_ERRORCODES_PUBLIC_H +#define BL_ERRORCODES_PUBLIC_H + +/* Bootloader Return Codes, Error only (0x00 through 0x9F) */ +#define BL_OK 0x00 // General - Success +#define BL_ERR_GENERIC 0x01 // Generic Error Code + +#endif /* BL_ERRORCODES_PUBLIC_H */
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Martin Roth (Code Review)