Change in coreboot[master]: mainboard/google/coral: Add USB2 phy setting override

[Tim Chen (Code Review)]

Tim Chen has uploaded this change for review. ( https://review.coreboot.org/21131

Change subject: mainboard/google/coral: Add USB2 phy setting override
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mainboard/google/coral: Add USB2 phy setting override

In order to pass type C USB2 eye diagram,
USB2 port#1 PHY register will need to be overridden.

port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2

BUG=b:64880573
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage

Change-Id: I86182969217046361fe915fb4c940bfad69cbf45
Signed-off-by: Tim Chen 
---
M src/mainboard/google/reef/variants/coral/devicetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/21131/1

diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb
index d5f546c..239d062 100644
--- a/src/mainboard/google/reef/variants/coral/devicetree.cb
+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb
@@ -116,6 +116,12 @@
    # Minimum SLP S3 assertion width 28ms.
    register "slp_s3_assertion_width_usecs" = "28000"

+	# Override USB2 PER PORT register (PORT 1)
+	register "usb2eye[1]" = "{
+		.Usb20PerPortPeTxiSet = 7,
+		.Usb20PerPortTxiSet = 2,
+	}"
+
    device domain 0 on
    	device pci 00.0 on  end	# - Host Bridge
    	device pci 00.1 on  end	# - DPTF