Change in coreboot[master]: mb/google/cherry: Add NOR-Flash support

[Rex-BC Chen (Code Review)]

Attention is currently required from: Yidi Lin.
Hello Yidi Lin,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/52872

to review the following change.

Change subject: mb/google/cherry: Add NOR-Flash support
......................................................................

mb/google/cherry: Add NOR-Flash support

TEST=boot to romstage on MT8195 EVB

Change-Id: I356e6b1cba3c078bf99e056b290476c7179e8ccf
Signed-off-by: Yidi Lin 
---
M src/mainboard/google/cherry/Kconfig
M src/mainboard/google/cherry/Makefile.inc
A src/mainboard/google/cherry/bootblock.c
M src/soc/mediatek/mt8195/Kconfig
M src/soc/mediatek/mt8195/Makefile.inc
A src/soc/mediatek/mt8195/include/soc/symbols.h
M src/soc/mediatek/mt8195/spi.c
7 files changed, 68 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/52872/1

diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig
index 8c7c093..bf46532 100644
--- a/src/mainboard/google/cherry/Kconfig
+++ b/src/mainboard/google/cherry/Kconfig
@@ -22,4 +22,10 @@
 config MAINBOARD_PART_NUMBER
    string
    default "Cherry" if BOARD_GOOGLE_CHERRY
+
+# On MT8195 the SPI flash is actually using a SPI-NOR controller with its own bus.
+# The number here should be a virtual value as (SPI_BUS_NUMBER + 1).
+config BOOT_DEVICE_SPI_FLASH_BUS
+	int
+	default 7
 endif
diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc
index 4831a39..a1aa2fd 100644
--- a/src/mainboard/google/cherry/Makefile.inc
+++ b/src/mainboard/google/cherry/Makefile.inc
@@ -1,4 +1,5 @@
 bootblock-y += memlayout.ld
+bootblock-y += bootblock.c
 bootblock-y += chromeos.c

verstage-y += memlayout.ld
diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c
new file mode 100644
index 0000000..6f61a82
--- /dev/null
+++ b/src/mainboard/google/cherry/bootblock.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/mmio.h>
+#include <soc/gpio.h>
+
+struct pad_func {
+	u8 pin_id;
+	u8 func;
+};
+
+#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func}
+
+static void nor_set_gpio_pinmux(void)
+{
+	const struct pad_func *ptr = NULL;
+
+	/* GPIO 140 ~ 143 */
+	struct pad_func nor_pinmux[] = {
+		PAD_FUNC(SPIM2_CSB, SPINOR_CS),
+		PAD_FUNC(SPIM2_CLK, SPINOR_CK),
+		PAD_FUNC(SPIM2_MO, SPINOR_IO0),
+		PAD_FUNC(SPIM2_MI, SPINOR_IO1),
+	};
+
+	ptr = nor_pinmux;
+	for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++) {
+		gpio_set_pull((gpio_t){.id = ptr[i].pin_id},
+				GPIO_PULL_ENABLE, GPIO_PULL_UP);
+		gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func);
+	}
+}
+
+void bootblock_mainboard_init(void)
+{
+	nor_set_gpio_pinmux();
+}
diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig
index 76329cd..bed3e04 100644
--- a/src/soc/mediatek/mt8195/Kconfig
+++ b/src/soc/mediatek/mt8195/Kconfig
@@ -17,4 +17,11 @@
    select VBOOT_SEPARATE_VERSTAGE
    select VBOOT_RETURN_FROM_VERSTAGE

+config FLASH_DUAL_READ
+	bool
+	default y
+	help
+	  When this option is enabled, the flash controller provides the ability
+	  to dual read mode.
+
 endif
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index b515c16..ad053fb 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -1,6 +1,7 @@
 ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y)

bootblock-y += bootblock.c
+bootblock-y += ../common/flash_controller.c
 bootblock-y += ../common/gpio.c gpio.c
 bootblock-y += ../common/mmu_operations.c
 bootblock-y += ../common/pll.c pll.c
@@ -9,6 +10,7 @@
 bootblock-y += ../common/uart.c
 bootblock-y += ../common/wdt.c

+verstage-y += ../common/flash_controller.c
 verstage-y += ../common/gpio.c gpio.c
 verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 verstage-y += ../common/timer.c timer.c
@@ -17,6 +19,7 @@

romstage-y += ../common/cbmem.c
 romstage-y += emi.c
+romstage-y += ../common/flash_controller.c
 romstage-y += ../common/gpio.c gpio.c
 romstage-y += ../common/pll.c pll.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
@@ -30,6 +33,7 @@
 romstage-y += ../common/mt6359p.c mt6359p.c

ramstage-y += emi.c
+ramstage-y += ../common/flash_controller.c
 ramstage-y += ../common/gpio.c gpio.c
 ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 ramstage-y += soc.c
diff --git a/src/soc/mediatek/mt8195/include/soc/symbols.h b/src/soc/mediatek/mt8195/include/soc/symbols.h
new file mode 100644
index 0000000..a7feee7
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/symbols.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8192_SYMBOLS_H_
+#define _SOC_MEDIATEK_MT8192_SYMBOLS_H_
+#include <symbols.h>
+
+DECLARE_REGION(dram_dma)
+
+#endif /* _SOC_MEDIATEK_MT8192_SYMBOLS_H_ */
diff --git a/src/soc/mediatek/mt8195/spi.c b/src/soc/mediatek/mt8195/spi.c
index fe7ad82..42564a6 100644
--- a/src/soc/mediatek/mt8195/spi.c
+++ b/src/soc/mediatek/mt8195/spi.c
@@ -3,6 +3,7 @@
 #include <device/mmio.h>
 #include <assert.h>
 #include <soc/addressmap.h>
+#include <soc/flash_controller_common.h>
 #include <soc/gpio.h>
 #include <soc/spi.h>

@@ -93,6 +94,7 @@

static const struct spi_ctrlr spi_flash_ctrlr = {
    .max_xfer_size = 65535,
+	.flash_probe = mtk_spi_flash_probe,
 };

const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
@@ -103,6 +105,8 @@
    },
    {
    	.ctrlr = &spi_flash_ctrlr,
+		.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
+		.bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
    },
 };