Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38981 )
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
xeonsp/skylake-sp: Add FSP SiliconInit invocation
Silicon Init is called at ramstage through chip enable function. This patch adds minimal skeleton chip ops.
Change-Id: I3e5eeb580207aa7c3d3ab02a3321b658e63c95d0 --- M src/cpu/intel/xeonsp/Kconfig M src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc A src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c 3 files changed, 103 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/38981/1
diff --git a/src/cpu/intel/xeonsp/Kconfig b/src/cpu/intel/xeonsp/Kconfig index 0c6c103..aa9579f 100644 --- a/src/cpu/intel/xeonsp/Kconfig +++ b/src/cpu/intel/xeonsp/Kconfig @@ -44,6 +44,10 @@ string default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/Server_M.fd"
+config FSP_S_FILE + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/Server_S.fd" + config PCR_BASE_ADDRESS hex default 0xfd000000 diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc b/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc index 42fb607..50da224 100644 --- a/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc +++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc @@ -13,6 +13,7 @@ ##
romstage-y += romstage.c +ramstage-y += chip.c
CPPFLAGS_common += -I$(src)/cpu/intel/xeonsp/include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c new file mode 100644 index 0000000..52488d8 --- /dev/null +++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <device/device.h> +#include <fsp/api.h> +#include <lib.h> + +static void skxsp_pci_domain_read_resources(struct device *dev) +{ +} + +static void skxsp_pci_domain_set_resources(struct device *dev) +{ +} + +static void skxsp_pci_domain_scan_bus(struct device *dev) +{ +} + +static struct device_operations pci_domain_ops = { + .read_resources = &skxsp_pci_domain_read_resources, + .set_resources = &skxsp_pci_domain_set_resources, + .scan_bus = &skxsp_pci_domain_scan_bus, +}; + +static void init_cpus(struct device *dev) +{ + /* not implemented yet */ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = init_cpus, + .scan_bus = NULL, +}; + +static void chip_init(void *data) +{ + printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); + fsp_silicon_init(false); +} + +static void chip_final(void *data) +{ + /* nothing implemented yet */ +} + +static void chip_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations cpu_intel_xeonsp_cpu_skylake_sp_ops = { + CHIP_NAME("Intel Skylake-SP") + .enable_dev = chip_enable_dev, + .init = chip_init, + .final = chip_final +}; + +void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) +{ + const struct microcode *microcode_file; + size_t microcode_len; + + /* Let FSP-S load ucode */ + microcode_file = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", + CBFS_TYPE_MICROCODE, µcode_len); + + if ((microcode_file != NULL) && (microcode_len != 0)) { + /* Update CPU Microcode patch base address/size */ + silupd->FspsConfig.PcdCpuMicrocodePatchBase = + (uint32_t)microcode_file; + silupd->FspsConfig.PcdCpuMicrocodePatchSize = + (uint32_t)microcode_len; + } +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38981 )
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38981/1/src/cpu/intel/xeonsp/cpu/sk... File src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38981/1/src/cpu/intel/xeonsp/cpu/sk... PS1, Line 67: if (dev->path.type == DEVICE_PATH_DOMAIN) { braces {} are not necessary for any arm of this statement
https://review.coreboot.org/c/coreboot/+/38981/1/src/cpu/intel/xeonsp/cpu/sk... PS1, Line 70: else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { else should follow close brace '}'
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38981
to look at the new patch set (#2).
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
xeonsp/skylake-sp: Add FSP SiliconInit invocation
Silicon Init is called at ramstage through chip enable function. This patch adds minimal skeleton chip ops.
Change-Id: I3e5eeb580207aa7c3d3ab02a3321b658e63c95d0 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/cpu/intel/xeonsp/Kconfig M src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc A src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c 3 files changed, 103 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/38981/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38981 )
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38981/2/src/cpu/intel/xeonsp/cpu/sk... File src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38981/2/src/cpu/intel/xeonsp/cpu/sk... PS2, Line 67: if (dev->path.type == DEVICE_PATH_DOMAIN) { braces {} are not necessary for any arm of this statement
https://review.coreboot.org/c/coreboot/+/38981/2/src/cpu/intel/xeonsp/cpu/sk... PS2, Line 70: else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { else should follow close brace '}'
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38981 )
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38981/3/src/cpu/intel/xeonsp/cpu/sk... File src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38981/3/src/cpu/intel/xeonsp/cpu/sk... PS3, Line 67: if (dev->path.type == DEVICE_PATH_DOMAIN) { braces {} are not necessary for any arm of this statement
https://review.coreboot.org/c/coreboot/+/38981/3/src/cpu/intel/xeonsp/cpu/sk... PS3, Line 70: else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { else should follow close brace '}'
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38981
to look at the new patch set (#4).
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
xeonsp/skylake-sp: Add FSP SiliconInit invocation
Silicon Init is called at ramstage through chip enable function. This patch adds minimal skeleton chip ops.
Change-Id: I3e5eeb580207aa7c3d3ab02a3321b658e63c95d0 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/cpu/intel/xeonsp/Kconfig M src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc A src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c 3 files changed, 102 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/38981/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38981 )
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38981/4/src/cpu/intel/xeonsp/cpu/sk... File src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38981/4/src/cpu/intel/xeonsp/cpu/sk... PS4, Line 67: if (dev->path.type == DEVICE_PATH_DOMAIN) { braces {} are not necessary for any arm of this statement
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38981 )
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38981/5/src/cpu/intel/xeonsp/cpu/sk... File src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38981/5/src/cpu/intel/xeonsp/cpu/sk... PS5, Line 67: if (dev->path.type == DEVICE_PATH_DOMAIN) { braces {} are not necessary for any arm of this statement
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38981 )
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38981/6/src/cpu/intel/xeonsp/cpu/sk... File src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38981/6/src/cpu/intel/xeonsp/cpu/sk... PS6, Line 67: if (dev->path.type == DEVICE_PATH_DOMAIN) { braces {} are not necessary for any arm of this statement
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38981 )
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38981/7/src/cpu/intel/xeonsp/cpu/sk... File src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38981/7/src/cpu/intel/xeonsp/cpu/sk... PS7, Line 67: if (dev->path.type == DEVICE_PATH_DOMAIN) { braces {} are not necessary for any arm of this statement
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38981
to look at the new patch set (#8).
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
xeonsp/skylake-sp: Add FSP SiliconInit invocation
Silicon Init is called at ramstage through chip enable function. This patch adds minimal skeleton chip ops.
Change-Id: I3e5eeb580207aa7c3d3ab02a3321b658e63c95d0 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/cpu/intel/xeonsp/Kconfig M src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc A src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c 3 files changed, 105 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/38981/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38981 )
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38981/8/src/cpu/intel/xeonsp/cpu/sk... File src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38981/8/src/cpu/intel/xeonsp/cpu/sk... PS8, Line 70: if (dev->path.type == DEVICE_PATH_DOMAIN) { braces {} are not necessary for any arm of this statement
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38981 )
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38981/9/src/cpu/intel/xeonsp/cpu/sk... File src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38981/9/src/cpu/intel/xeonsp/cpu/sk... PS9, Line 70: if (dev->path.type == DEVICE_PATH_DOMAIN) { braces {} are not necessary for any arm of this statement
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38981 )
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38981/10/src/cpu/intel/xeonsp/cpu/s... File src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38981/10/src/cpu/intel/xeonsp/cpu/s... PS10, Line 70: if (dev->path.type == DEVICE_PATH_DOMAIN) { braces {} are not necessary for any arm of this statement
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38981 )
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
Patch Set 10: Code-Review+1
Andrey Petrov has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38981 )
Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ......................................................................
Abandoned
killing in favor of new patchset
-
Andrey Petrov (Code Review) -
Angel Pons (Code Review)
-
build bot (Jenkins) (Code Review)