Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41942 )
Change subject: broadwell: Relocate functions and prototypes ......................................................................
broadwell: Relocate functions and prototypes
Move the code around so that it aligns with Haswell.
Change-Id: I3ae1bd0298bbb5b04787ae5bf14f32b77b47046d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell.h M src/cpu/intel/broadwell/broadwell_early_init.c R src/cpu/intel/broadwell/broadwell_init.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/romstage.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/variant.h M src/northbridge/intel/broadwell/Makefile.inc A src/northbridge/intel/broadwell/acpi.c M src/northbridge/intel/broadwell/broadwell.h R src/northbridge/intel/broadwell/early_init.c A src/northbridge/intel/broadwell/northbridge.c M src/northbridge/intel/broadwell/raminit.c A src/northbridge/intel/broadwell/raminit.h M src/northbridge/intel/broadwell/refcode.c A src/northbridge/intel/broadwell/refcode.h M src/northbridge/intel/broadwell/report_platform.c D src/northbridge/intel/broadwell/romstage.h M src/northbridge/intel/broadwell/systemagent.c M src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/lpc.c M src/southbridge/intel/wildcatpoint/pch.h M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c M src/southbridge/intel/wildcatpoint/ramstage.h A src/southbridge/intel/wildcatpoint/romstage.h 31 files changed, 824 insertions(+), 762 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/41942/1
diff --git a/src/cpu/intel/broadwell/Makefile.inc b/src/cpu/intel/broadwell/Makefile.inc index 453b879..ad5dc5b 100644 --- a/src/cpu/intel/broadwell/Makefile.inc +++ b/src/cpu/intel/broadwell/Makefile.inc @@ -16,9 +16,10 @@
ramstage-y += acpi.c
+ramstage-y += broadwell_init.c + ramstage-y += chip.c
-ramstage-y += cpu.c ramstage-y += cpu_info.c smm-y += cpu_info.c
diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c index bd4eb63..a63914c 100644 --- a/src/cpu/intel/broadwell/acpi.c +++ b/src/cpu/intel/broadwell/acpi.c @@ -147,151 +147,26 @@ return cores; }
-void acpi_init_gnvs(global_nvs_t *gnvs) +static void generate_C_state_entries(void) { - /* Set unknown wake source */ - gnvs->pm1i = -1; + acpi_cstate_t map[3]; + int *set; + int i;
- /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); + config_t *config = config_of_soc();
-#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif + if (config->s0ix_enable) + set = cstate_set_s0ix; + else + set = cstate_set_non_s0ix;
-#if CONFIG(CHROMEOS) - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if CONFIG(EC_GOOGLE_CHROMEEC) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; -#endif -} + for (i = 0; i < 3; i++) { + memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i].ctype = i + 1; + }
-unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, 255); - return current; -} - -void acpi_fill_in_fadt(acpi_fadt_t *fadt) -{ - const uint16_t pmbase = ACPI_BASE_ADDRESS; - - fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS(0); - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - /* - * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. - * The bit_width field intentionally overflows here. - * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which - * seems to work fine on Linux 5.0 and Windows 10. - */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; - - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + /* Generate C-state tables */ + acpigen_write_CST_package(map, ARRAY_SIZE(map)); }
static acpi_tstate_t tss_table_fine[] = { @@ -346,28 +221,6 @@ ARRAY_SIZE(tss_table_coarse), tss_table_coarse); }
-static void generate_C_state_entries(void) -{ - acpi_cstate_t map[3]; - int *set; - int i; - - config_t *config = config_of_soc(); - - if (config->s0ix_enable) - set = cstate_set_s0ix; - else - set = cstate_set_non_s0ix; - - for (i = 0; i < 3; i++) { - memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); - map[i].ctype = i + 1; - } - - /* Generate C-state tables */ - acpigen_write_CST_package(map, ARRAY_SIZE(map)); -} - static int calculate_power(int tdp, int p1_ratio, int ratio) { u32 m; @@ -540,70 +393,6 @@ acpigen_write_processor_cnot(cores_per_package); }
-static unsigned long acpi_fill_dmar(unsigned long current) -{ - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); - const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; - const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; - const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; - const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; - - /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ - if (igfx_dev && igfx_dev->enabled && gfxvtbar - && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { - unsigned long tmp = current; - - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - - acpi_dmar_drhd_fixup(tmp, current); - - /* Add RMRR entry */ - tmp = current; - - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - acpi_dmar_rmrr_fixup(tmp, current); - } - - /* VTVC0BAR has to be set, enabled, and in 32-bit space */ - if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { - const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); - size_t i; - for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, - 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); - acpi_dmar_drhd_fixup(tmp, current); - } - - return current; -} - -unsigned long northbridge_write_acpi_tables(const struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - /* Create DMAR table only if we have VT-d capability. */ - const u32 capid0_a = pci_read_config32(dev, CAPID0_A); - if (capid0_a & VTD_DISABLE) - return current; - - acpi_dmar_t *const dmar = (acpi_dmar_t *)current; - printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); - current += dmar->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, dmar); - - return current; -} - unsigned long acpi_madt_irq_overrides(unsigned long current) { int sci = acpi_sci_irq(); diff --git a/src/cpu/intel/broadwell/bootblock.c b/src/cpu/intel/broadwell/bootblock.c index 3290eee..fbaea86 100644 --- a/src/cpu/intel/broadwell/bootblock.c +++ b/src/cpu/intel/broadwell/bootblock.c @@ -7,9 +7,10 @@ #include <cpu/x86/mtrr.h> #include <halt.h> #include <southbridge/intel/wildcatpoint/rcba.h> -#include <cpu/intel/broadwell/broadwell.h> #include <delay.h>
+#include <cpu/intel/broadwell/broadwell.h> + static void set_flex_ratio_to_tdp_nominal(void) { msr_t flex_ratio, msr; diff --git a/src/cpu/intel/broadwell/broadwell.h b/src/cpu/intel/broadwell/broadwell.h index 5654e0a..9e62eea 100644 --- a/src/cpu/intel/broadwell/broadwell.h +++ b/src/cpu/intel/broadwell/broadwell.h @@ -108,4 +108,19 @@ u32 cpu_stepping(void); int cpu_is_ult(void);
+#include <northbridge/intel/broadwell/pei_data.h> + +struct chipset_power_state; +struct romstage_params { + struct chipset_power_state *power_state; + struct pei_data pei_data; +}; + +void set_max_freq(void); + +void mainboard_pre_raminit(struct romstage_params *params); +void mainboard_post_raminit(struct romstage_params *params); + +void broadwell_init_cpus(struct device *dev); + #endif diff --git a/src/cpu/intel/broadwell/broadwell_early_init.c b/src/cpu/intel/broadwell/broadwell_early_init.c index 4fd23f6..b093ece 100644 --- a/src/cpu/intel/broadwell/broadwell_early_init.c +++ b/src/cpu/intel/broadwell/broadwell_early_init.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/intel/broadwell/broadwell.h> -#include <northbridge/intel/broadwell/romstage.h>
u32 cpu_family_model(void) { diff --git a/src/cpu/intel/broadwell/cpu.c b/src/cpu/intel/broadwell/broadwell_init.c similarity index 97% rename from src/cpu/intel/broadwell/cpu.c rename to src/cpu/intel/broadwell/broadwell_init.c index f8132b5..8c74394 100644 --- a/src/cpu/intel/broadwell/cpu.c +++ b/src/cpu/intel/broadwell/broadwell_init.c @@ -1,29 +1,41 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <arch/cpu.h> #include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/mp.h> +#include <cpu/intel/broadwell/broadwell.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/x86/name.h> #include <cpu/x86/smm.h> #include <delay.h> +#include <device/device.h> #include <intelblocks/cpulib.h> -#include <cpu/intel/broadwell/broadwell.h> +#include <northbridge/intel/broadwell/broadwell.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <southbridge/intel/wildcatpoint/ramstage.h> #include <southbridge/intel/wildcatpoint/rcba.h> -#include <northbridge/intel/broadwell/broadwell.h> #include <southbridge/intel/wildcatpoint/soc_chip.h> -#include <cpu/intel/common/common.h> +#include <string.h> +#include <types.h> + +/** power_limit_time_sec_to_msr **/ + +/** power_limit_time_msr_to_sec **/ + +/** haswell_family_model **/ + +/** haswell_stepping **/ + +/** haswell_is_ult **/
/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly @@ -230,6 +242,10 @@ RCBA32(PMSYNC_CONFIG2) = pmsync2; }
+/** cpu_config_tdp_levels **/ + +/** set_power_limits **/ + static void configure_c_states(void) { msr_t msr; diff --git a/src/cpu/intel/broadwell/chip.c b/src/cpu/intel/broadwell/chip.c index 443faf4..c769a80 100644 --- a/src/cpu/intel/broadwell/chip.c +++ b/src/cpu/intel/broadwell/chip.c @@ -2,8 +2,11 @@
#include <device/device.h> #include <device/pci.h> +#include <cpu/intel/broadwell/broadwell.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <southbridge/intel/wildcatpoint/acpi.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pch.h> #include <southbridge/intel/wildcatpoint/ramstage.h> #include <southbridge/intel/wildcatpoint/soc_chip.h>
diff --git a/src/cpu/intel/broadwell/romstage.c b/src/cpu/intel/broadwell/romstage.c index 35bb592..e33ae9f 100644 --- a/src/cpu/intel/broadwell/romstage.c +++ b/src/cpu/intel/broadwell/romstage.c @@ -10,11 +10,14 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <timestamp.h> +#include <cpu/intel/broadwell/broadwell.h> #include <southbridge/intel/wildcatpoint/gpio.h> #include <southbridge/intel/wildcatpoint/me.h> #include <northbridge/intel/broadwell/pei_data.h> #include <southbridge/intel/wildcatpoint/pm.h> -#include <northbridge/intel/broadwell/romstage.h> +#include <northbridge/intel/broadwell/raminit.h> +#include <southbridge/intel/wildcatpoint/romstage.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <southbridge/intel/wildcatpoint/spi.h>
void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index 1540299..cf6b447 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -2,9 +2,9 @@
#include <console/console.h> #include <ec/google/chromeec/ec.h> +#include <cpu/intel/broadwell/broadwell.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> -#include <northbridge/intel/broadwell/romstage.h> #include <variant/spd.h> #include "variant.h"
diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h index 9853aa2..20873f0 100644 --- a/src/mainboard/google/auron/variant.h +++ b/src/mainboard/google/auron/variant.h @@ -4,7 +4,7 @@ #define VARIANT_H
#include <device/device.h> -#include <northbridge/intel/broadwell/romstage.h> +#include <cpu/intel/broadwell/broadwell.h>
int variant_smbios_data(struct device *dev, int *handle, unsigned long *current); diff --git a/src/northbridge/intel/broadwell/Makefile.inc b/src/northbridge/intel/broadwell/Makefile.inc index 51cf4a8..69ea826 100644 --- a/src/northbridge/intel/broadwell/Makefile.inc +++ b/src/northbridge/intel/broadwell/Makefile.inc @@ -4,6 +4,10 @@
bootblock-y += bootblock.c
+ramstage-y += acpi.c + +romstage-y += early_init.c + ramstage-y += finalize.c
ramstage-y += igd.c @@ -13,12 +17,13 @@ postcar-y += memmap.c ramstage-y += minihd.c
+ramstage-y += northbridge.c + ramstage-y += pei_data.c romstage-y += pei_data.c
romstage-y += raminit.c romstage-y += report_platform.c -romstage-y += romstage.c
ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
diff --git a/src/northbridge/intel/broadwell/acpi.c b/src/northbridge/intel/broadwell/acpi.c new file mode 100644 index 0000000..df08537 --- /dev/null +++ b/src/northbridge/intel/broadwell/acpi.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <console/console.h> +#include <acpi/acpi.h> +#include <device/device.h> +#include <device/pci_ops.h> +#include <northbridge/intel/broadwell/broadwell.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + MCFG_BASE_ADDRESS, 0, 0, 255); + return current; +} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; + const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; + const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; + const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; + + /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ + if (igfx_dev && igfx_dev->enabled && gfxvtbar + && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + + /* Add RMRR entry */ + tmp = current; + + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + + /* VTVC0BAR has to be set, enabled, and in 32-bit space */ + if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + const unsigned long tmp = current; + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, + 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + size_t i; + for (i = 0; i < 8; ++i) + current += acpi_create_dmar_ds_msi_hpet(current, + 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); + acpi_dmar_drhd_fixup(tmp, current); + } + + return current; +} + +unsigned long northbridge_write_acpi_tables(const struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + /* Create DMAR table only if we have VT-d capability. */ + const u32 capid0_a = pci_read_config32(dev, CAPID0_A); + if (capid0_a & VTD_DISABLE) + return current; + + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} diff --git a/src/northbridge/intel/broadwell/broadwell.h b/src/northbridge/intel/broadwell/broadwell.h index 5f4ad6c..1a8e6cf 100644 --- a/src/northbridge/intel/broadwell/broadwell.h +++ b/src/northbridge/intel/broadwell/broadwell.h @@ -126,4 +126,13 @@ uintptr_t sa_get_tolud_base(void); uintptr_t sa_get_gsm_base(void);
+void report_platform_info(void); + +void systemagent_early_init(void); + +#include <device/device.h> + +unsigned long northbridge_write_acpi_tables(const struct device *dev, unsigned long current, + struct acpi_rsdp *rsdp); + #endif diff --git a/src/northbridge/intel/broadwell/romstage.c b/src/northbridge/intel/broadwell/early_init.c similarity index 97% rename from src/northbridge/intel/broadwell/romstage.c rename to src/northbridge/intel/broadwell/early_init.c index 064c203..e1bbcc8 100644 --- a/src/northbridge/intel/broadwell/romstage.c +++ b/src/northbridge/intel/broadwell/early_init.c @@ -6,7 +6,6 @@ #include <reg_script.h> #include <southbridge/intel/wildcatpoint/iomap.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> -#include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h>
static const struct reg_script systemagent_early_init_script[] = { diff --git a/src/northbridge/intel/broadwell/northbridge.c b/src/northbridge/intel/broadwell/northbridge.c new file mode 100644 index 0000000..5122fed --- /dev/null +++ b/src/northbridge/intel/broadwell/northbridge.c @@ -0,0 +1,433 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <acpi/acpi.h> +#include <device/pci_ops.h> +#include <stdint.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/power_limit.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <cpu/intel/broadwell/broadwell.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <northbridge/intel/broadwell/broadwell.h> + +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, + u32 *len) +{ + u32 pciexbar_reg; + + *base = 0; + *len = 0; + + pciexbar_reg = pci_read_config32(dev, index); + + if (!(pciexbar_reg & (1 << 0))) + return 0; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: // 256MB + *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| + (1 << 28)); + *len = 256 * 1024 * 1024; + return 1; + case 1: // 128M + *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| + (1 << 28)|(1 << 27)); + *len = 128 * 1024 * 1024; + return 1; + case 2: // 64M + *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| + (1 << 28)|(1 << 27)|(1 << 26)); + *len = 64 * 1024 * 1024; + return 1; + } + + return 0; +} + +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) +{ + u32 bar; + + bar = pci_read_config32(dev, index); + + /* If not enabled don't report it. */ + if (!(bar & 0x1)) + return 0; + + /* Knock down the enable bit. */ + *base = bar & ~1; + + return 1; +} + +/* There are special BARs that actually are programmed in the MCHBAR. These + * Intel special features, but they do consume resources that need to be + * accounted for. */ +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, + u32 *len) +{ + u32 bar; + + bar = MCHBAR32(index); + + /* If not enabled don't report it. */ + if (!(bar & 0x1)) + return 0; + + /* Knock down the enable bit. */ + *base = bar & ~1; + + return 1; +} + +struct fixed_mmio_descriptor { + unsigned int index; + u32 size; + int (*get_resource)(struct device *dev, unsigned int index, + u32 *base, u32 *size); + const char *description; +}; + +struct fixed_mmio_descriptor mc_fixed_resources[] = { + { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, + { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, + { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, + { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, + { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, + { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, +}; + +/* + * Add all known fixed MMIO ranges that hang off the host bridge/memory + * controller device. + */ +static void mc_add_fixed_mmio_resources(struct device *dev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { + u32 base; + u32 size; + struct resource *resource; + unsigned int index; + + size = mc_fixed_resources[i].size; + index = mc_fixed_resources[i].index; + if (!mc_fixed_resources[i].get_resource(dev, index, + &base, &size)) + continue; + + resource = new_resource(dev, mc_fixed_resources[i].index); + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; + resource->base = base; + resource->size = size; + printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", + __func__, mc_fixed_resources[i].description, index, + (unsigned long)base, (unsigned long)(base + size - 1)); + } +} + +/* Host Memory Map: + * + * +--------------------------+ TOUUD + * | | + * +--------------------------+ 4GiB + * | PCI Address Space | + * +--------------------------+ TOLUD (also maps into MC address space) + * | iGD | + * +--------------------------+ BDSM + * | GTT | + * +--------------------------+ BGSM + * | TSEG | + * +--------------------------+ TSEGMB + * | Usage DRAM | + * +--------------------------+ 0 + * + * Some of the base registers above can be equal making the size of those + * regions 0. The reason is because the memory controller internally subtracts + * the base registers from each other to determine sizes of the regions. In + * other words, the memory map is in a fixed order no matter what. + */ + +struct map_entry { + int reg; + int is_64_bit; + int is_limit; + const char *description; +}; + +static void read_map_entry(struct device *dev, struct map_entry *entry, + uint64_t *result) +{ + uint64_t value; + uint64_t mask; + + /* All registers are on a 1MiB granularity. */ + mask = ((1ULL<<20)-1); + mask = ~mask; + + value = 0; + + if (entry->is_64_bit) { + value = pci_read_config32(dev, entry->reg + 4); + value <<= 32; + } + + value |= pci_read_config32(dev, entry->reg); + value &= mask; + + if (entry->is_limit) + value |= ~mask; + + *result = value; +} + +#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ + { \ + .reg = reg_, \ + .is_64_bit = is_64_, \ + .is_limit = is_limit_, \ + .description = desc_, \ + } + +#define MAP_ENTRY_BASE_64(reg_, desc_) \ + MAP_ENTRY(reg_, 1, 0, desc_) +#define MAP_ENTRY_LIMIT_64(reg_, desc_) \ + MAP_ENTRY(reg_, 1, 1, desc_) +#define MAP_ENTRY_BASE_32(reg_, desc_) \ + MAP_ENTRY(reg_, 0, 0, desc_) + +enum { + TOM_REG, + TOUUD_REG, + MESEG_BASE_REG, + MESEG_LIMIT_REG, + REMAP_BASE_REG, + REMAP_LIMIT_REG, + TOLUD_REG, + BGSM_REG, + BDSM_REG, + TSEG_REG, + // Must be last. + NUM_MAP_ENTRIES +}; + +static struct map_entry memory_map[NUM_MAP_ENTRIES] = { + [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), + [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), + [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), + [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), + [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), + [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), + [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), + [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), + [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), + [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), +}; + +static void mc_read_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) + read_map_entry(dev, &memory_map[i], &values[i]); +} + +static void mc_report_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) { + printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", + memory_map[i].description, values[i]); + } + /* One can validate the BDSM and BGSM against the GGC. */ + printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); +} + +static void mc_add_dram_resources(struct device *dev, int *resource_cnt) +{ + unsigned long base_k, size_k; + unsigned long touud_k; + unsigned long index; + struct resource *resource; + uint64_t mc_values[NUM_MAP_ENTRIES]; + unsigned long dpr_size = 0; + u32 dpr_reg; + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + + /* Read in the MAP registers and report their values. */ + mc_read_map_entries(dev, &mc_values[0]); + mc_report_map_entries(dev, &mc_values[0]); + + /* + * DMA Protected Range can be reserved below TSEG for PCODE patch + * or TXT/BootGuard related data. Rather than report a base address + * the DPR register reports the TOP of the region, which is the same + * as TSEG base. The region size is reported in MiB in bits 11:4. + */ + dpr_reg = pci_read_config32(sa_dev, DPR); + if (dpr_reg & DPR_EPM) { + dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; + printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); + } + + /* + * These are the host memory ranges that should be added: + * - 0 -> 0xa0000: cacheable + * - 0xc0000 -> TSEG : cacheable + * - TESG -> BGSM: cacheable with standard MTRRs and reserved + * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved + * - 4GiB -> TOUUD: cacheable + * + * The default SMRAM space is reserved so that the range doesn't + * have to be saved during S3 Resume. Once marked reserved the OS + * cannot use the memory. This is a bit of an odd place to reserve + * the region, but the CPU devices don't have dev_ops->read_resources() + * called on them. + * + * The range 0xa0000 -> 0xc0000 does not have any resources + * associated with it to handle legacy VGA memory. If this range + * is not omitted the mtrr code will setup the area as cacheable + * causing VGA access to not work. + * + * The TSEG region is mapped as cacheable so that one can perform + * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes + * precedence over the existing MTRRs covering this region. + * + * It should be noted that cacheable entry types need to be added in + * order. The reason is that the current MTRR code assumes this and + * falls over itself if it isn't. + * + * The resource index starts low and should not meet or exceed + * PCI_BASE_ADDRESS_0. + */ + index = *resource_cnt; + + /* 0 - > 0xa0000 */ + base_k = 0; + size_k = (0xa0000 >> 10) - base_k; + ram_resource(dev, index++, base_k, size_k); + + /* 0xc0000 -> TSEG - DPR */ + base_k = 0xc0000 >> 10; + size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; + size_k -= dpr_size >> 10; + ram_resource(dev, index++, base_k, size_k); + + /* TSEG - DPR -> BGSM */ + resource = new_resource(dev, index++); + resource->base = mc_values[TSEG_REG] - dpr_size; + resource->size = mc_values[BGSM_REG] - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; + + /* BGSM -> TOLUD */ + resource = new_resource(dev, index++); + resource->base = mc_values[BGSM_REG]; + resource->size = mc_values[TOLUD_REG] - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; + + /* 4GiB -> TOUUD */ + base_k = 4096 * 1024; /* 4GiB */ + touud_k = mc_values[TOUUD_REG] >> 10; + size_k = touud_k - base_k; + if (touud_k > base_k) + ram_resource(dev, index++, base_k, size_k); + + /* Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xfffff: RAM + */ + mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), + (0x100000 - 0xc0000) >> 10); + + if (CONFIG(CHROMEOS)) + chromeos_reserve_ram_oops(dev, index++); + + *resource_cnt = index; +} + +static void systemagent_read_resources(struct device *dev) +{ + int index = 0; + const bool vtd_capable = + !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); + + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* Add all fixed MMIO resources. */ + mc_add_fixed_mmio_resources(dev); + + /* Add VT-d MMIO resources if capable */ + if (vtd_capable) { + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, + GFXVT_BASE_SIZE / KiB); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, + VTVC0_BASE_SIZE / KiB); + } + + /* Calculate and add DRAM resources. */ + mc_add_dram_resources(dev, &index); +} + +static void systemagent_init(struct device *dev) +{ + struct soc_power_limits_config *config; + u8 bios_reset_cpl, pair; + + /* Enable Power Aware Interrupt Routing */ + pair = MCHBAR8(MCH_PAIR); + pair &= ~0x7; /* Clear 2:0 */ + pair |= 0x4; /* Fixed Priority */ + MCHBAR8(MCH_PAIR) = pair; + + /* + * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialized memory and power management + */ + bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); + bios_reset_cpl |= 3; + MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; + printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); + + /* Configure turbo power limits 1ms after reset complete bit */ + mdelay(1); + config = config_of_soc(); + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config); +} + +static struct device_operations systemagent_ops = { + .read_resources = systemagent_read_resources, + .acpi_fill_ssdt = generate_cpu_entries, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = systemagent_init, + .ops_pci = &broadwell_pci_ops, +}; + +static const unsigned short systemagent_ids[] = { + 0x0a04, /* Haswell ULT */ + 0x1604, /* Broadwell-U/Y */ + 0x1610, /* Broadwell-H Desktop */ + 0x1614, /* Broadwell-H Mobile */ + 0 +}; + +static const struct pci_driver systemagent_driver __pci_driver = { + .ops = &systemagent_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = systemagent_ids +}; diff --git a/src/northbridge/intel/broadwell/raminit.c b/src/northbridge/intel/broadwell/raminit.c index d40c2a3..9e8d8ad 100644 --- a/src/northbridge/intel/broadwell/raminit.c +++ b/src/northbridge/intel/broadwell/raminit.c @@ -9,17 +9,54 @@ #include <memory_info.h> #include <mrc_cache.h> #include <string.h> -#if CONFIG(EC_GOOGLE_CHROMEEC) -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#endif #include <vendorcode/google/chromeos/chromeos.h> #include <southbridge/intel/wildcatpoint/iomap.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> #include <southbridge/intel/wildcatpoint/pm.h> -#include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h> +#include <northbridge/intel/broadwell/raminit.h> + +/* + * Dump in the log memory controller configuration as read from the memory + * controller registers. + */ +void report_memory_config(void) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + int i; + + addr_decoder_common = MCHBAR32(0x5000); + addr_decode_ch[0] = MCHBAR32(0x5004); + addr_decode_ch[1] = MCHBAR32(0x5008); + + printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", + (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", + addr_decoder_common & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3); + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", + i, ch_conf); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", + ((ch_conf >> 22) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " rank interleave %s\n", + ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); + } +}
/* * Find PEI executable in coreboot filesystem and execute it. diff --git a/src/northbridge/intel/broadwell/raminit.h b/src/northbridge/intel/broadwell/raminit.h new file mode 100644 index 0000000..7f324b8 --- /dev/null +++ b/src/northbridge/intel/broadwell/raminit.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef RAMINIT_H +#define RAMINIT_H + +#include "pei_data.h" + +void raminit(struct pei_data *pei_data); +void report_memory_config(void); + +#endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/broadwell/refcode.c b/src/northbridge/intel/broadwell/refcode.c index 13be8b6..11df686 100644 --- a/src/northbridge/intel/broadwell/refcode.c +++ b/src/northbridge/intel/broadwell/refcode.c @@ -11,6 +11,7 @@ #include <stage_cache.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> +#include <northbridge/intel/broadwell/refcode.h> #include <southbridge/intel/wildcatpoint/pm.h> #include <southbridge/intel/wildcatpoint/ramstage.h>
diff --git a/src/northbridge/intel/broadwell/refcode.h b/src/northbridge/intel/broadwell/refcode.h new file mode 100644 index 0000000..80219eb --- /dev/null +++ b/src/northbridge/intel/broadwell/refcode.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BROADWELL_REFCODE_H_ +#define _BROADWELL_REFCODE_H_ + +#if CONFIG(HAVE_REFCODE_BLOB) +void broadwell_run_reference_code(void); +#else +static inline void broadwell_run_reference_code(void) { } +#endif + +#endif /* _BROADWELL_REFCODE_H_ */ diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c index 3ac4ece..95d9c99 100644 --- a/src/northbridge/intel/broadwell/report_platform.c +++ b/src/northbridge/intel/broadwell/report_platform.c @@ -9,7 +9,6 @@ #include <cpu/intel/broadwell/broadwell.h> #include <southbridge/intel/wildcatpoint/pch.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> -#include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h>
static struct { @@ -184,44 +183,3 @@ report_pch_info(); report_igd_info(); } - -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ -void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[2]; - int i; - - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} diff --git a/src/northbridge/intel/broadwell/romstage.h b/src/northbridge/intel/broadwell/romstage.h deleted file mode 100644 index 275938a..0000000 --- a/src/northbridge/intel/broadwell/romstage.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _BROADWELL_ROMSTAGE_H_ -#define _BROADWELL_ROMSTAGE_H_ - -#include <stdint.h> -#include <northbridge/intel/broadwell/pei_data.h> - -struct chipset_power_state; -struct romstage_params { - struct chipset_power_state *power_state; - struct pei_data pei_data; -}; - -void mainboard_pre_raminit(struct romstage_params *params); -void mainboard_post_raminit(struct romstage_params *params); - -void raminit(struct pei_data *pei_data); - -struct chipset_power_state; -struct chipset_power_state *fill_power_state(void); -void report_platform_info(void); -void report_memory_config(void); - -void set_max_freq(void); - -void systemagent_early_init(void); -void pch_early_init(void); -void pch_uart_init(void); -void intel_early_me_status(void); - -#endif diff --git a/src/northbridge/intel/broadwell/systemagent.c b/src/northbridge/intel/broadwell/systemagent.c index 67d78cf..ee5e836 100644 --- a/src/northbridge/intel/broadwell/systemagent.c +++ b/src/northbridge/intel/broadwell/systemagent.c @@ -1,19 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <console/console.h> -#include <acpi/acpi.h> #include <device/pci_ops.h> -#include <stdint.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <intelblocks/power_limit.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <cpu/intel/broadwell/broadwell.h> -#include <southbridge/intel/wildcatpoint/iomap.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> -#include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/broadwell.h>
u8 systemagent_revision(void) @@ -35,419 +26,3 @@ /* Bit 0 is lock bit, not part of address */ return pci_read_config32(sa_dev, BGSM) & ~1; } - -static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, - u32 *len) -{ - u32 pciexbar_reg; - - *base = 0; - *len = 0; - - pciexbar_reg = pci_read_config32(dev, index); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)); - *len = 256 * 1024 * 1024; - return 1; - case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; - case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; - } - - return 0; -} - -static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 bar; - - bar = pci_read_config32(dev, index); - - /* If not enabled don't report it. */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit. */ - *base = bar & ~1; - - return 1; -} - -/* There are special BARs that actually are programmed in the MCHBAR. These - * Intel special features, but they do consume resources that need to be - * accounted for. */ -static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, - u32 *len) -{ - u32 bar; - - bar = MCHBAR32(index); - - /* If not enabled don't report it. */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit. */ - *base = bar & ~1; - - return 1; -} - -struct fixed_mmio_descriptor { - unsigned int index; - u32 size; - int (*get_resource)(struct device *dev, unsigned int index, - u32 *base, u32 *size); - const char *description; -}; - -struct fixed_mmio_descriptor mc_fixed_resources[] = { - { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, - { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, - { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, - { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, - { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, - { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, -}; - -/* - * Add all known fixed MMIO ranges that hang off the host bridge/memory - * controller device. - */ -static void mc_add_fixed_mmio_resources(struct device *dev) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { - u32 base; - u32 size; - struct resource *resource; - unsigned int index; - - size = mc_fixed_resources[i].size; - index = mc_fixed_resources[i].index; - if (!mc_fixed_resources[i].get_resource(dev, index, - &base, &size)) - continue; - - resource = new_resource(dev, mc_fixed_resources[i].index); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; - resource->base = base; - resource->size = size; - printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", - __func__, mc_fixed_resources[i].description, index, - (unsigned long)base, (unsigned long)(base + size - 1)); - } -} - -/* Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. - */ - -struct map_entry { - int reg; - int is_64_bit; - int is_limit; - const char *description; -}; - -static void read_map_entry(struct device *dev, struct map_entry *entry, - uint64_t *result) -{ - uint64_t value; - uint64_t mask; - - /* All registers are on a 1MiB granularity. */ - mask = ((1ULL<<20)-1); - mask = ~mask; - - value = 0; - - if (entry->is_64_bit) { - value = pci_read_config32(dev, entry->reg + 4); - value <<= 32; - } - - value |= pci_read_config32(dev, entry->reg); - value &= mask; - - if (entry->is_limit) - value |= ~mask; - - *result = value; -} - -#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ - { \ - .reg = reg_, \ - .is_64_bit = is_64_, \ - .is_limit = is_limit_, \ - .description = desc_, \ - } - -#define MAP_ENTRY_BASE_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 0, desc_) -#define MAP_ENTRY_LIMIT_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 1, desc_) -#define MAP_ENTRY_BASE_32(reg_, desc_) \ - MAP_ENTRY(reg_, 0, 0, desc_) - -enum { - TOM_REG, - TOUUD_REG, - MESEG_BASE_REG, - MESEG_LIMIT_REG, - REMAP_BASE_REG, - REMAP_LIMIT_REG, - TOLUD_REG, - BGSM_REG, - BDSM_REG, - TSEG_REG, - // Must be last. - NUM_MAP_ENTRIES -}; - -static struct map_entry memory_map[NUM_MAP_ENTRIES] = { - [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), - [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), - [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), - [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), - [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), - [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), - [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), - [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), - [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), -}; - -static void mc_read_map_entries(struct device *dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) - read_map_entry(dev, &memory_map[i], &values[i]); -} - -static void mc_report_map_entries(struct device *dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { - printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", - memory_map[i].description, values[i]); - } - /* One can validate the BDSM and BGSM against the GGC. */ - printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); -} - -static void mc_add_dram_resources(struct device *dev, int *resource_cnt) -{ - unsigned long base_k, size_k; - unsigned long touud_k; - unsigned long index; - struct resource *resource; - uint64_t mc_values[NUM_MAP_ENTRIES]; - unsigned long dpr_size = 0; - u32 dpr_reg; - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - - /* Read in the MAP registers and report their values. */ - mc_read_map_entries(dev, &mc_values[0]); - mc_report_map_entries(dev, &mc_values[0]); - - /* - * DMA Protected Range can be reserved below TSEG for PCODE patch - * or TXT/BootGuard related data. Rather than report a base address - * the DPR register reports the TOP of the region, which is the same - * as TSEG base. The region size is reported in MiB in bits 11:4. - */ - dpr_reg = pci_read_config32(sa_dev, DPR); - if (dpr_reg & DPR_EPM) { - dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; - printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); - } - - /* - * These are the host memory ranges that should be added: - * - 0 -> 0xa0000: cacheable - * - 0xc0000 -> TSEG : cacheable - * - TESG -> BGSM: cacheable with standard MTRRs and reserved - * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved - * - 4GiB -> TOUUD: cacheable - * - * The default SMRAM space is reserved so that the range doesn't - * have to be saved during S3 Resume. Once marked reserved the OS - * cannot use the memory. This is a bit of an odd place to reserve - * the region, but the CPU devices don't have dev_ops->read_resources() - * called on them. - * - * The range 0xa0000 -> 0xc0000 does not have any resources - * associated with it to handle legacy VGA memory. If this range - * is not omitted the mtrr code will setup the area as cacheable - * causing VGA access to not work. - * - * The TSEG region is mapped as cacheable so that one can perform - * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes - * precedence over the existing MTRRs covering this region. - * - * It should be noted that cacheable entry types need to be added in - * order. The reason is that the current MTRR code assumes this and - * falls over itself if it isn't. - * - * The resource index starts low and should not meet or exceed - * PCI_BASE_ADDRESS_0. - */ - index = *resource_cnt; - - /* 0 - > 0xa0000 */ - base_k = 0; - size_k = (0xa0000 >> 10) - base_k; - ram_resource(dev, index++, base_k, size_k); - - /* 0xc0000 -> TSEG - DPR */ - base_k = 0xc0000 >> 10; - size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; - size_k -= dpr_size >> 10; - ram_resource(dev, index++, base_k, size_k); - - /* TSEG - DPR -> BGSM */ - resource = new_resource(dev, index++); - resource->base = mc_values[TSEG_REG] - dpr_size; - resource->size = mc_values[BGSM_REG] - resource->base; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; - - /* BGSM -> TOLUD */ - resource = new_resource(dev, index++); - resource->base = mc_values[BGSM_REG]; - resource->size = mc_values[TOLUD_REG] - resource->base; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; - - /* 4GiB -> TOUUD */ - base_k = 4096 * 1024; /* 4GiB */ - touud_k = mc_values[TOUUD_REG] >> 10; - size_k = touud_k - base_k; - if (touud_k > base_k) - ram_resource(dev, index++, base_k, size_k); - - /* Reserve everything between A segment and 1MB: - * - * 0xa0000 - 0xbffff: legacy VGA - * 0xc0000 - 0xfffff: RAM - */ - mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); - reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); - - if (CONFIG(CHROMEOS)) - chromeos_reserve_ram_oops(dev, index++); - - *resource_cnt = index; -} - -static void systemagent_read_resources(struct device *dev) -{ - int index = 0; - const bool vtd_capable = - !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); - - /* Read standard PCI resources. */ - pci_dev_read_resources(dev); - - /* Add all fixed MMIO resources. */ - mc_add_fixed_mmio_resources(dev); - - /* Add VT-d MMIO resources if capable */ - if (vtd_capable) { - mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, - GFXVT_BASE_SIZE / KiB); - mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, - VTVC0_BASE_SIZE / KiB); - } - - /* Calculate and add DRAM resources. */ - mc_add_dram_resources(dev, &index); -} - -static void systemagent_init(struct device *dev) -{ - struct soc_power_limits_config *config; - u8 bios_reset_cpl, pair; - - /* Enable Power Aware Interrupt Routing */ - pair = MCHBAR8(MCH_PAIR); - pair &= ~0x7; /* Clear 2:0 */ - pair |= 0x4; /* Fixed Priority */ - MCHBAR8(MCH_PAIR) = pair; - - /* - * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU - * that BIOS has initialized memory and power management - */ - bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); - bios_reset_cpl |= 3; - MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; - printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); - - /* Configure turbo power limits 1ms after reset complete bit */ - mdelay(1); - config = config_of_soc(); - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config); -} - -static struct device_operations systemagent_ops = { - .read_resources = systemagent_read_resources, - .acpi_fill_ssdt = generate_cpu_entries, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = systemagent_init, - .ops_pci = &broadwell_pci_ops, -}; - -static const unsigned short systemagent_ids[] = { - 0x0a04, /* Haswell ULT */ - 0x1604, /* Broadwell-U/Y */ - 0x1610, /* Broadwell-H Desktop */ - 0x1614, /* Broadwell-H Mobile */ - 0 -}; - -static const struct pci_driver systemagent_driver __pci_driver = { - .ops = &systemagent_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = systemagent_ids -}; diff --git a/src/southbridge/intel/wildcatpoint/acpi.h b/src/southbridge/intel/wildcatpoint/acpi.h index 618b627..c747a4b 100644 --- a/src/southbridge/intel/wildcatpoint/acpi.h +++ b/src/southbridge/intel/wildcatpoint/acpi.h @@ -12,9 +12,8 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10
-void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); -unsigned long northbridge_write_acpi_tables(const struct device *dev, - unsigned long current, struct acpi_rsdp *rsdp); +void acpi_fill_in_fadt(acpi_fadt_t *fadt); + #endif diff --git a/src/southbridge/intel/wildcatpoint/early_pch.c b/src/southbridge/intel/wildcatpoint/early_pch.c index e8cb8aa..00ad55f 100644 --- a/src/southbridge/intel/wildcatpoint/early_pch.c +++ b/src/southbridge/intel/wildcatpoint/early_pch.c @@ -11,7 +11,7 @@ #include <southbridge/intel/wildcatpoint/pci_devs.h> #include <southbridge/intel/wildcatpoint/pm.h> #include <southbridge/intel/wildcatpoint/rcba.h> -#include <northbridge/intel/broadwell/romstage.h> +#include <southbridge/intel/wildcatpoint/romstage.h> #include <southbridge/intel/wildcatpoint/smbus.h> #include <southbridge/intel/wildcatpoint/soc_chip.h>
diff --git a/src/southbridge/intel/wildcatpoint/early_smbus.c b/src/southbridge/intel/wildcatpoint/early_smbus.c index 6f4d226..0b43cc2 100644 --- a/src/southbridge/intel/wildcatpoint/early_smbus.c +++ b/src/southbridge/intel/wildcatpoint/early_smbus.c @@ -6,7 +6,6 @@ #include <southbridge/intel/wildcatpoint/iomap.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> #include <southbridge/intel/wildcatpoint/smbus.h> -#include <northbridge/intel/broadwell/romstage.h>
static const struct reg_script smbus_init_script[] = { /* Set SMBUS I/O base address */ diff --git a/src/southbridge/intel/wildcatpoint/lpc.c b/src/southbridge/intel/wildcatpoint/lpc.c index b7f1fe3..e1b2bec 100644 --- a/src/southbridge/intel/wildcatpoint/lpc.c +++ b/src/southbridge/intel/wildcatpoint/lpc.c @@ -15,6 +15,7 @@ #include <cbmem.h> #include <reg_script.h> #include <string.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <southbridge/intel/wildcatpoint/gpio.h> #include <southbridge/intel/wildcatpoint/iobp.h> #include <southbridge/intel/wildcatpoint/iomap.h> @@ -595,6 +596,146 @@ } }
+void acpi_init_gnvs(global_nvs_t *gnvs) +{ + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + +#if CONFIG(CONSOLE_CBMEM) + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); +#endif + +#if CONFIG(CHROMEOS) + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); +#if CONFIG(EC_GOOGLE_CHROMEEC) + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; +#endif + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; +#endif +} + +void acpi_fill_in_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 32; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} + static unsigned long broadwell_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) diff --git a/src/southbridge/intel/wildcatpoint/pch.h b/src/southbridge/intel/wildcatpoint/pch.h index 59b5b18..dfe3560 100644 --- a/src/southbridge/intel/wildcatpoint/pch.h +++ b/src/southbridge/intel/wildcatpoint/pch.h @@ -29,5 +29,6 @@ int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_disable_devfn(struct device *dev); +void broadwell_pch_enable_dev(struct device *dev);
#endif diff --git a/src/southbridge/intel/wildcatpoint/power_state.c b/src/southbridge/intel/wildcatpoint/power_state.c index 8522caa..419fd4e 100644 --- a/src/southbridge/intel/wildcatpoint/power_state.c +++ b/src/southbridge/intel/wildcatpoint/power_state.c @@ -13,7 +13,7 @@ #include <southbridge/intel/wildcatpoint/lpc.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> #include <southbridge/intel/wildcatpoint/pm.h> -#include <northbridge/intel/broadwell/romstage.h> +#include <southbridge/intel/wildcatpoint/romstage.h>
static struct chipset_power_state power_state;
diff --git a/src/southbridge/intel/wildcatpoint/ramstage.c b/src/southbridge/intel/wildcatpoint/ramstage.c index 8859261..5d8ec0e 100644 --- a/src/southbridge/intel/wildcatpoint/ramstage.c +++ b/src/southbridge/intel/wildcatpoint/ramstage.c @@ -4,6 +4,7 @@ #include <cbmem.h> #include <device/device.h> #include <string.h> +#include <northbridge/intel/broadwell/refcode.h> #include <southbridge/intel/wildcatpoint/nvs.h> #include <southbridge/intel/wildcatpoint/pm.h> #include <southbridge/intel/wildcatpoint/ramstage.h> diff --git a/src/southbridge/intel/wildcatpoint/ramstage.h b/src/southbridge/intel/wildcatpoint/ramstage.h index b50cd19..1343dad 100644 --- a/src/southbridge/intel/wildcatpoint/ramstage.h +++ b/src/southbridge/intel/wildcatpoint/ramstage.h @@ -7,14 +7,6 @@ #include <southbridge/intel/wildcatpoint/soc_chip.h>
void broadwell_init_pre_device(void *chip_info); -void broadwell_init_cpus(struct device *dev); -void broadwell_pch_enable_dev(struct device *dev); - -#if CONFIG(HAVE_REFCODE_BLOB) -void broadwell_run_reference_code(void); -#else -static inline void broadwell_run_reference_code(void) { } -#endif
extern struct pci_operations broadwell_pci_ops;
diff --git a/src/southbridge/intel/wildcatpoint/romstage.h b/src/southbridge/intel/wildcatpoint/romstage.h new file mode 100644 index 0000000..d780e99 --- /dev/null +++ b/src/southbridge/intel/wildcatpoint/romstage.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _WILDCATPOINT_ROMSTAGE_H_ +#define _WILDCATPOINT_ROMSTAGE_H_ + +struct chipset_power_state; +struct chipset_power_state *fill_power_state(void); + +void pch_early_init(void); +void pch_uart_init(void); +void intel_early_me_status(void); + +#endif
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41942
to look at the new patch set (#3).
Change subject: broadwell: Relocate functions and prototypes ......................................................................
broadwell: Relocate functions and prototypes
Move the code around so that it aligns with Haswell.
Change-Id: I3ae1bd0298bbb5b04787ae5bf14f32b77b47046d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell.h M src/cpu/intel/broadwell/broadwell_early_init.c R src/cpu/intel/broadwell/broadwell_init.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/romstage.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/romstage.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/northbridge/intel/broadwell/Makefile.inc A src/northbridge/intel/broadwell/acpi.c M src/northbridge/intel/broadwell/broadwell.h R src/northbridge/intel/broadwell/early_init.c A src/northbridge/intel/broadwell/northbridge.c M src/northbridge/intel/broadwell/raminit.c A src/northbridge/intel/broadwell/raminit.h M src/northbridge/intel/broadwell/refcode.c A src/northbridge/intel/broadwell/refcode.h M src/northbridge/intel/broadwell/report_platform.c D src/northbridge/intel/broadwell/romstage.h M src/northbridge/intel/broadwell/systemagent.c M src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/lpc.c M src/southbridge/intel/wildcatpoint/pch.h M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c M src/southbridge/intel/wildcatpoint/ramstage.h A src/southbridge/intel/wildcatpoint/romstage.h 42 files changed, 828 insertions(+), 773 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/41942/3
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41942
to look at the new patch set (#6).
Change subject: broadwell: Relocate functions and prototypes ......................................................................
broadwell: Relocate functions and prototypes
Move the code around so that it aligns with Haswell.
Change-Id: I3ae1bd0298bbb5b04787ae5bf14f32b77b47046d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell.h M src/cpu/intel/broadwell/broadwell_early_init.c R src/cpu/intel/broadwell/broadwell_init.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/romstage.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/romstage.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/northbridge/intel/broadwell/Makefile.inc A src/northbridge/intel/broadwell/acpi.c M src/northbridge/intel/broadwell/broadwell.h R src/northbridge/intel/broadwell/early_init.c A src/northbridge/intel/broadwell/northbridge.c M src/northbridge/intel/broadwell/raminit.c A src/northbridge/intel/broadwell/raminit.h M src/northbridge/intel/broadwell/refcode.c A src/northbridge/intel/broadwell/refcode.h M src/northbridge/intel/broadwell/report_platform.c D src/northbridge/intel/broadwell/romstage.h M src/northbridge/intel/broadwell/systemagent.c M src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/lpc.c M src/southbridge/intel/wildcatpoint/pch.h M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c M src/southbridge/intel/wildcatpoint/ramstage.h A src/southbridge/intel/wildcatpoint/romstage.h 42 files changed, 827 insertions(+), 772 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/41942/6
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41942
to look at the new patch set (#9).
Change subject: broadwell: Relocate functions and prototypes ......................................................................
broadwell: Relocate functions and prototypes
Move the code around so that it aligns with Haswell.
Change-Id: I3ae1bd0298bbb5b04787ae5bf14f32b77b47046d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell.h M src/cpu/intel/broadwell/broadwell_early_init.c R src/cpu/intel/broadwell/broadwell_init.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/romstage.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/romstage.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/northbridge/intel/broadwell/Makefile.inc A src/northbridge/intel/broadwell/acpi.c M src/northbridge/intel/broadwell/broadwell.h R src/northbridge/intel/broadwell/early_init.c A src/northbridge/intel/broadwell/northbridge.c M src/northbridge/intel/broadwell/raminit.c A src/northbridge/intel/broadwell/raminit.h M src/northbridge/intel/broadwell/refcode.c A src/northbridge/intel/broadwell/refcode.h M src/northbridge/intel/broadwell/report_platform.c D src/northbridge/intel/broadwell/romstage.h M src/northbridge/intel/broadwell/systemagent.c M src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/lpc.c M src/southbridge/intel/wildcatpoint/pch.h M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c M src/southbridge/intel/wildcatpoint/ramstage.h A src/southbridge/intel/wildcatpoint/romstage.h 42 files changed, 827 insertions(+), 772 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/41942/9
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41942
to look at the new patch set (#10).
Change subject: broadwell: Relocate functions and prototypes ......................................................................
broadwell: Relocate functions and prototypes
Move the code around so that it aligns with Haswell.
Change-Id: I3ae1bd0298bbb5b04787ae5bf14f32b77b47046d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell.h M src/cpu/intel/broadwell/broadwell_early_init.c R src/cpu/intel/broadwell/broadwell_init.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/romstage.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/romstage.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/northbridge/intel/broadwell/Makefile.inc A src/northbridge/intel/broadwell/acpi.c M src/northbridge/intel/broadwell/broadwell.h R src/northbridge/intel/broadwell/early_init.c A src/northbridge/intel/broadwell/northbridge.c M src/northbridge/intel/broadwell/raminit.c A src/northbridge/intel/broadwell/raminit.h M src/northbridge/intel/broadwell/refcode.c A src/northbridge/intel/broadwell/refcode.h M src/northbridge/intel/broadwell/report_platform.c D src/northbridge/intel/broadwell/romstage.h M src/northbridge/intel/broadwell/systemagent.c M src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/lpc.c M src/southbridge/intel/wildcatpoint/pch.h M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c M src/southbridge/intel/wildcatpoint/ramstage.h A src/southbridge/intel/wildcatpoint/romstage.h 42 files changed, 827 insertions(+), 772 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/41942/10
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41942
to look at the new patch set (#13).
Change subject: broadwell: Relocate functions and prototypes ......................................................................
broadwell: Relocate functions and prototypes
Move the code around so that it aligns with Haswell.
Change-Id: I3ae1bd0298bbb5b04787ae5bf14f32b77b47046d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell.h M src/cpu/intel/broadwell/broadwell_early_init.c R src/cpu/intel/broadwell/broadwell_init.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/romstage.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/romstage.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/northbridge/intel/broadwell/Makefile.inc A src/northbridge/intel/broadwell/acpi.c M src/northbridge/intel/broadwell/broadwell.h R src/northbridge/intel/broadwell/early_init.c A src/northbridge/intel/broadwell/northbridge.c M src/northbridge/intel/broadwell/raminit.c A src/northbridge/intel/broadwell/raminit.h M src/northbridge/intel/broadwell/refcode.c A src/northbridge/intel/broadwell/refcode.h M src/northbridge/intel/broadwell/report_platform.c D src/northbridge/intel/broadwell/romstage.h M src/northbridge/intel/broadwell/systemagent.c M src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/lpc.c M src/southbridge/intel/wildcatpoint/pch.h M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c M src/southbridge/intel/wildcatpoint/ramstage.h A src/southbridge/intel/wildcatpoint/romstage.h 42 files changed, 827 insertions(+), 772 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/41942/13
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41942
to look at the new patch set (#17).
Change subject: broadwell: Relocate functions and prototypes ......................................................................
broadwell: Relocate functions and prototypes
Move the code around so that it aligns with Haswell.
Change-Id: I3ae1bd0298bbb5b04787ae5bf14f32b77b47046d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell.h M src/cpu/intel/broadwell/broadwell_early_init.c R src/cpu/intel/broadwell/broadwell_init.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/romstage.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/romstage.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/northbridge/intel/broadwell/Makefile.inc A src/northbridge/intel/broadwell/acpi.c M src/northbridge/intel/broadwell/broadwell.h R src/northbridge/intel/broadwell/early_init.c A src/northbridge/intel/broadwell/northbridge.c M src/northbridge/intel/broadwell/raminit.c A src/northbridge/intel/broadwell/raminit.h M src/northbridge/intel/broadwell/refcode.c A src/northbridge/intel/broadwell/refcode.h M src/northbridge/intel/broadwell/report_platform.c D src/northbridge/intel/broadwell/romstage.h M src/northbridge/intel/broadwell/systemagent.c M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/lpc.c M src/southbridge/intel/wildcatpoint/pch.h M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c M src/southbridge/intel/wildcatpoint/ramstage.h A src/southbridge/intel/wildcatpoint/romstage.h 41 files changed, 826 insertions(+), 770 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/41942/17
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41942 )
Change subject: broadwell: Relocate functions and prototypes ......................................................................
Abandoned
-
Angel Pons (Code Review)