Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71603 )
Change subject: Revert "{cpu/nb}/amd/family16: Remove platform" ......................................................................
Revert "{cpu/nb}/amd/family16: Remove platform"
This reverts commit 49af4f7f9197e559b2c7142129441679bb1d24a2.
Change-Id: I78d41a626228baed81b467e284268c9a5cc57aca Signed-off-by: Damien Zammit damien@zamaudio.com --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/agesa/Makefile.inc A src/cpu/amd/agesa/family16kb/Kconfig A src/cpu/amd/agesa/family16kb/Makefile.inc A src/cpu/amd/agesa/family16kb/acpi/cpu.asl A src/cpu/amd/agesa/family16kb/chip_name.c A src/cpu/amd/agesa/family16kb/fixme.c A src/cpu/amd/agesa/family16kb/model_16_init.c A src/northbridge/amd/agesa/Makefile.inc A src/northbridge/amd/agesa/family16kb/Kconfig A src/northbridge/amd/agesa/family16kb/Makefile.inc A src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl A src/northbridge/amd/agesa/family16kb/acpi_tables.c A src/northbridge/amd/agesa/family16kb/chip.h A src/northbridge/amd/agesa/family16kb/dimmSpd.c A src/northbridge/amd/agesa/family16kb/northbridge.c A src/northbridge/amd/agesa/family16kb/pci_devs.h A src/northbridge/amd/agesa/family16kb/state_machine.c M src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c 20 files changed, 1,342 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/71603/1
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index d46d2ed..f6c4f16 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -2,6 +2,7 @@
config CPU_AMD_AGESA bool + default y if CPU_AMD_AGESA_FAMILY16_KB default n select ARCH_X86 select DRIVERS_AMD_PI @@ -43,3 +44,5 @@ from non-volatile memory.
endif # CPU_AMD_AGESA + +source "src/cpu/amd/agesa/family16kb/Kconfig" diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 4cacc51..5d8f6df 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only + +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb + romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig new file mode 100644 index 0000000..60bf64f --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config CPU_AMD_AGESA_FAMILY16_KB + bool + select SMM_ASEG + select X86_AMD_FIXED_MTRRS + +if CPU_AMD_AGESA_FAMILY16_KB + +config FORCE_AM1_SOCKET_SUPPORT + bool + default n + help + Force AGESA to ignore package type mismatch between CPU and northbridge + in memory code. This enables Socket AM1 support with current AGESA + version for Kabini platform. + Enable this option only if you have Socket AM1 board. + Note that the AGESA release shipped with coreboot does not officially + support the AM1 socket. Selecting this option might damage your hardware. + +endif diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc new file mode 100644 index 0000000..9464372 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += fixme.c + +ramstage-y += fixme.c +ramstage-y += chip_name.c +ramstage-y += model_16_init.c + +subdirs-y += ../../mtrr diff --git a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl new file mode 100644 index 0000000..d589ae8 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Processor Object + * + */ +Scope (_SB) {/* define processor scope */ + Device (P000) { + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + + Device (P001) { + Name(_HID, "ACPI0007") + Name(_UID, 1) + } + + Device (P002) { + Name(_HID, "ACPI0007") + Name(_UID, 2) + } + + Device (P003) { + Name(_HID, "ACPI0007") + Name(_UID, 3) + } + + Device (P004) { + Name(_HID, "ACPI0007") + Name(_UID, 4) + } + + Device (P005) { + Name(_HID, "ACPI0007") + Name(_UID, 5) + } + + Device (P006) { + Name(_HID, "ACPI0007") + Name(_UID, 6) + } + + Device (P007) { + Name(_HID, "ACPI0007") + Name(_UID, 7) + } +} /* End _SB scope */ diff --git a/src/cpu/amd/agesa/family16kb/chip_name.c b/src/cpu/amd/agesa/family16kb/chip_name.c new file mode 100644 index 0000000..0ca021c --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/chip_name.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +struct chip_operations cpu_amd_agesa_family16kb_ops = { + CHIP_NAME("AMD CPU Family 16h Model 00h-0Fh") +}; diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c new file mode 100644 index 0000000..da2744c --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/hpet.h> +#include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> +#include <amdlib.h> + +void amd_initcpuio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +} diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c new file mode 100644 index 0000000..0f11136 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <amdblocks/cpu.h> +#include <amdblocks/smm.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <device/device.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +static void model_16_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Model 16 Init.\n"); + + msr_t msr; + int msrno; +#if CONFIG(LOGICAL_CPUS) + u32 siblings; +#endif + + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. + */ + disable_cache(); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs + msr.lo = msr.hi = 0; + wrmsr(MTRR_FIX_16K_A0000, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + wrmsr(MTRR_FIX_64K_00000, msr); + wrmsr(MTRR_FIX_16K_80000, msr); + for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) + wrmsr(msrno, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + if (acpi_is_wakeup_s3()) + restore_mtrr(); + + x86_mtrr_check(); + enable_cache(); + + /* zero the machine check error status registers */ + mca_clear_status(); + +#if CONFIG(LOGICAL_CPUS) + siblings = get_cpu_count() - 1; // minus BSP + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + /* Write protect SMM space with SMMLOCK. */ + lock_smm(); +} + +static struct device_operations cpu_dev_ops = { + .init = model_16_init, +}; + +static const struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x700f00 }, /* KB-A0 */ + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc new file mode 100644 index 0000000..f586623 --- /dev/null +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y) + +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb + +endif diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig new file mode 100644 index 0000000..8cf919a --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB + bool + select LEGACY_SMP_INIT + select RESOURCE_ALLOCATOR_V3 + +if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config ECAM_MMCONF_BASE_ADDRESS + default 0xF8000000 + +config ECAM_MMCONF_BUS_NUMBER + default 64 + +config VGA_BIOS_ID + string + default "1002,9830" + help + The default VGA BIOS PCI vendor/device ID should be set to the + result of the map_oprom_vendev() function in northbridge.c. + +endif # NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc new file mode 100644 index 0000000..e387ee5 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += dimmSpd.c + +ramstage-y += northbridge.c +ramstage-y += acpi_tables.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl new file mode 100644 index 0000000..a635247 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Note: Only need HID on Primary Bus */ +External (TOM1) +External (TOM2) +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ + +/* Describe the Northbridge devices */ + +Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ +{ + Return(Zero) +} + +Method(_STA, 0, NotSerialized) +{ + Return(0x0B) /* Status is visible */ +} + +Method(_PRT,0, NotSerialized) +{ + If(PICM) + { + Return(APR0) /* APIC mode */ + } + Return (PR0) /* PIC Mode */ +} + +Device(AMRT) { + Name(_ADR, 0x00000000) +} /* end AMRT */ + +/* Gpp 0 */ +Device(PBR4) { + Name(_ADR, 0x00020001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR4 */ + +/* Gpp 1 */ +Device(PBR5) { + Name(_ADR, 0x00020002) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR5 */ + +/* Gpp 2 */ +Device(PBR6) { + Name(_ADR, 0x00020003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR6 */ + +/* Gpp 3 */ +Device(PBR7) { + Name(_ADR, 0x00020004) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR7 */ + +/* Gpp 4 */ +Device(PBR8) { + Name(_ADR, 0x00020005) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS8) } /* APIC mode */ + Return (PS8) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +Device(K10M) { + Name (_ADR, 0x00180003) + #include <soc/amd/common/acpi/thermal_zone.asl> +} diff --git a/src/northbridge/amd/agesa/family16kb/acpi_tables.c b/src/northbridge/amd/agesa/family16kb/acpi_tables.c new file mode 100644 index 0000000..cf88cfa --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/acpi_tables.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <arch/ioapic.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + /* TODO: Remove the hardcode */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS + 1, + 0xFEC20000, 24); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/northbridge/amd/agesa/family16kb/chip.h b/src/northbridge/amd/agesa/family16kb/chip.h new file mode 100644 index 0000000..239bc69 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/chip.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _NB_AGESA_CHIP_H_ +#define _NB_AGESA_CHIP_H_ + +struct northbridge_amd_agesa_family16kb_config +{ + u8 spdAddrLookup[2][2][4]; +}; + +#endif diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c new file mode 100644 index 0000000..1f9d970 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_def.h> +#include <device/device.h> + +/* warning: Porting.h includes an open #pragma pack(1) */ +#include <Porting.h> +#include <AGESA.h> +#include "chip.h" + +#include <northbridge/amd/agesa/dimmSpd.h> + +/** + * Gets the SMBus address for an SPD from the array in devicetree.cb + * then read the SPD into the supplied buffer. + */ +AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) +{ + UINT8 spdAddress; + + DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2); + if (dev == NULL) + return AGESA_ERROR; + + DEVTREE_CONST struct northbridge_amd_agesa_family16kb_config *config = dev->chip_info; + if (config == NULL) + return AGESA_ERROR; + + if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) + return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) + return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) + return AGESA_ERROR; + + spdAddress = config->spdAddrLookup + [info->SocketId][info->MemChannelId][info->DimmId]; + + if (spdAddress == 0) + return AGESA_ERROR; + + int err = hudson_readSpd(spdAddress, (void *)info->Buffer, DDR3_SPD_SIZE); + if (err) + return AGESA_ERROR; + return AGESA_SUCCESS; +} diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c new file mode 100644 index 0000000..250c491 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -0,0 +1,741 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/pci_ops.h> +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <lib.h> +#include <cpu/cpu.h> +#include <cpu/x86/lapic.h> +#include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> +#include <Porting.h> +#include <AGESA.h> +#include <Options.h> +#include <Topology.h> +#include <northbridge/amd/nb_common.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#define MAX_NODE_NUMS MAX_NODES + +static unsigned int node_nums; +static unsigned int sblink; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; +static unsigned int fx_devs = 0; + +static struct device *get_node_pci(u32 nodeid, u32 fn) +{ + return pcidev_on_root(DEV_CDB + nodeid, fn); +} + +static void get_fx_devs(void) +{ + int i; + for (i = 0; i < MAX_NODE_NUMS; i++) { + __f0_dev[i] = get_node_pci(i, 0); + __f1_dev[i] = get_node_pci(i, 1); + __f2_dev[i] = get_node_pci(i, 2); + __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i + 1; + } + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + die("Cannot find 0:0x18.[0|1]\n"); + } + printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); +} + +static u32 f1_read_config32(unsigned int reg) +{ + if (fx_devs == 0) + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} + +static void f1_write_config32(unsigned int reg, u32 value) +{ + int i; + if (fx_devs == 0) + get_fx_devs(); + for (i = 0; i < fx_devs; i++) { + struct device *dev; + dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) +{ + u32 temp; + + if (fx_devs == 0) + get_fx_devs(); + + + temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] + if (!(temp & 1)) + return 0; // this memory range is not enabled + /* + * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits + * for physical address and the convert to KiB by shifting 10 bits left + */ + *basek = ((temp & 0xffff0000)) >> (10 - 8); + /* + * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but + * ORed with 0xffff to get real limit before shifting. + */ + temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] + *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); + *limitk += 1; // round up last byte + + return 1; +} + +static u32 amdfam16_nodeid(struct device *dev) +{ + return (dev->path.pci.devfn >> 3) - DEV_CDB; +} + +static void set_vga_enable_reg(u32 nodeid, u32 linkn) +{ + u32 val; + + val = 1 | (nodeid << 4) | (linkn << 12); + /* it will routing + * (1)mmio 0xa0000:0xbffff + * (2)io 0x3b0:0x3bb, 0x3c0:0x3df + */ + f1_write_config32(0xf4, val); + +} + +static void read_resources(struct device *dev) +{ + /* + * This MMCONF resource must be reserved in the PCI_DOMAIN. + * It is not honored by the coreboot resource allocator if it is in + * the APIC_CLUSTER. + */ + mmconf_resource(dev, MMIO_CONF_BASE); + + /* There should be no BAR. */ +} + +/** + * I tried to reuse the resource allocation code in set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void create_vga_resource(struct device *dev, unsigned int nodeid) +{ + struct bus *link; + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG(MULTIPLE_VGA_ADAPTERS) + extern struct device *vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary, link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); + set_vga_enable_reg(nodeid, sblink); +} + +static void set_resources(struct device *dev) +{ + unsigned int nodeid; + + /* Find the nodeid */ + nodeid = amdfam16_nodeid(dev); + + create_vga_resource(dev, nodeid); //TODO: do we need this? +} + +static unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, + addr + 2, *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, + addr + 2, *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + +static void northbridge_fill_ssdt_generator(const struct device *device) +{ + msr_t msr; + char pscope[] = "\_SB.PCI0"; + + acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_pop_len(); +} + +static void patch_ssdt_processor_scope(acpi_header_t *ssdt) +{ + unsigned int len = ssdt->length - sizeof(acpi_header_t); + unsigned int i; + + for (i = sizeof(acpi_header_t); i < len; i++) { + /* Search for _PR_ scope and replace it with _SB_ */ + if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) + *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; + } + /* Recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); +} + +static unsigned long agesa_write_acpi_tables(const struct device *device, + unsigned long current, + acpi_rsdp_t *rsdp) +{ + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *alib; + acpi_header_t *ivrs; + acpi_hest_t *hest; + + /* HEST */ + current = ALIGN_UP(current, 8); + hest = (acpi_hest_t *)current; + acpi_write_hest(hest, acpi_fill_hest); + acpi_add_table(rsdp, hest); + current += hest->header.length; + + current = ALIGN_UP(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs != NULL) { + memcpy((void *)current, ivrs, ivrs->length); + ivrs = (acpi_header_t *)current; + current += ivrs->length; + acpi_add_table(rsdp, ivrs); + } else { + printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); + } + + /* SRAT */ + current = ALIGN_UP(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *)current; + current += srat->header.length; + acpi_add_table(rsdp, srat); + } else { + printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + } + + /* SLIT */ + current = ALIGN_UP(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *)current; + current += slit->header.length; + acpi_add_table(rsdp, slit); + } else { + printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + } + + /* ALIB */ + current = ALIGN_UP(current, 16); + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + alib = (acpi_header_t *)current; + current += alib->length; + acpi_add_table(rsdp, (void *)alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + + /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ + /* SSDT */ + current = ALIGN_UP(current, 16); + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); + if (ssdt != NULL) { + patch_ssdt_processor_scope(ssdt); + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *)current; + current += ssdt->length; + } + else { + printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + } + acpi_add_table(rsdp, ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + + return current; +} + +static struct device_operations northbridge_operations = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt = northbridge_fill_ssdt_generator, + .write_acpi_tables = agesa_write_acpi_tables, +}; + +static const struct pci_driver family16_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VID_AMD, + .device = PCI_DID_AMD_16H_MODEL_000F_NB_HT, +}; + +static const struct pci_driver family10_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VID_AMD, + .device = PCI_DID_AMD_10H_NB_HT, +}; + +static void fam16_finalize(void *chip_info) +{ + struct device *dev; + u32 value; + dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + /* disable No Snoop */ + dev = pcidev_on_root(1, 1); + if (dev != NULL) { + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); + } +} + +struct chip_operations northbridge_amd_agesa_family16kb_ops = { + CHIP_NAME("AMD FAM16 Northbridge") + .enable_dev = 0, + .final = fam16_finalize, +}; + +static void domain_read_resources(struct device *dev) +{ + unsigned int reg; + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xd8; reg += 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned int nodeid, reg_link; + struct device *reg_dev; + if (reg < 0xc0) { // mmio + nodeid = (limit & 0xf) + (base & 0x30); + } else { // io + nodeid = (limit & 0xf) + ((base >> 4) & 0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + + pci_domain_read_resources(dev); +} + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +struct hw_mem_hole_info { + unsigned int hole_startk; + int node_id; +}; +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + for (i = 0; i < node_nums; i++) { + resource_t basek, limitk; + u32 hole; + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node + hole = pci_read_config32(__f1_dev[i], 0xf0); + if (hole & 2) { // we find the hole + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + + /* We need to double check if there is special set on base reg and limit reg + * are not continuous instead of hole, it will find out its hole_startk. + */ + if (mem_hole.node_id == -1) { + resource_t limitk_pri = 0; + for (i = 0; i < node_nums; i++) { + resource_t base_k, limit_k; + if (!get_dram_base_limit(i, &base_k, &limit_k)) + continue; // no memory on this node + if (base_k > 4 * 1024 * 1024) break; // don't need to go to check + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G + mem_hole.node_id = i; + break; //only one hole + } + limitk_pri = limit_k; + } + } + return mem_hole; +} +#endif + +static void domain_set_resources(struct device *dev) +{ + unsigned long mmio_basek; + u32 pci_tolm; + int i, idx; + struct bus *link; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; +#endif + + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = find_pci_tolm(link); + } + + // FIXME handle interleaved nodes. If you fix this here, please fix + // amdk8, too. + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) - 1); + + // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + // MMIO hole. If you fix this here, please fix amdk8, too. + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64 * 1024) - 1); + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + /* if the hw mem hole is already set in raminit stage, here we will compare + * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will + * use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + + mem_hole = get_hw_mem_hole_info(); + + // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) + mmio_basek = mem_hole.hole_startk; +#endif + + idx = 0x10; + for (i = 0; i < node_nums; i++) { + resource_t basek, limitk, sizek; // 4 1T + + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node + + sizek = limitk - basek; + + /* See if we need a hole from 0xa0000 (640K) to 0xbffff (768K) */ + if (basek < 640 && sizek > 768) { + ram_resource_kb(dev, (idx | i), basek, 640 - basek); + idx += 0x10; + basek = 768; + sizek = limitk - basek; + } + + //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + + /* split the region to accommodate pci memory space */ + if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) { + if (basek <= mmio_basek) { + unsigned int pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek > 0) { + ram_resource_kb(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4 * 1024 * 1024) { + sizek = 0; + } + else { + uint64_t topmem2 = amd_topmem2(); + basek = 4 * 1024 * 1024; + sizek = topmem2 / 1024 - basek; + } + } + + ram_resource_kb(dev, (idx | i), basek, sizek); + idx += 0x10; + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + i, mmio_basek, basek, limitk); + } + + add_uma_resource_below_tolm(dev, 7); + + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); + } + } +} + +static const char *domain_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + return NULL; +} + +static struct device_operations pci_domain_ops = { + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .scan_bus = pci_domain_scan_bus, + .acpi_name = domain_acpi_name, +}; + +static void sysconf_init(struct device *dev) // first node +{ + sblink = (pci_read_config32(dev, 0x64) >> 8) & 7; // don't forget sublink1 + node_nums = ((pci_read_config32(dev, 0x60) >> 4) & 7) + 1; //NodeCnt[2:0] +} + +static void cpu_bus_scan(struct device *dev) +{ + struct bus *cpu_bus; + struct device *dev_mc; + int i, j; + int coreid_bits; + int core_max = 0; + unsigned int ApicIdCoreIdSize; + unsigned int core_nums; + int siblings = 0; + unsigned int family; + + dev_mc = pcidev_on_root(DEV_CDB, 0); + if (!dev_mc) { + printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); + die(""); + } + sysconf_init(dev_mc); + + /* Get Max Number of cores(MNC) */ + coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; + core_max = 1 << (coreid_bits & 0x000F); //mnc + + ApicIdCoreIdSize = ((cpuid_ecx(0x80000008) >> 12) & 0xF); + if (ApicIdCoreIdSize) { + core_nums = (1 << ApicIdCoreIdSize) - 1; + } else { + core_nums = 3; //quad core + } + + /* Find which cpus are present */ + cpu_bus = dev->link_list; + for (i = 0; i < node_nums; i++) { + struct device *cdb_dev; + unsigned int devn; + struct bus *pbus; + + devn = DEV_CDB + i; + pbus = dev_mc->bus; + + /* Find the cpu's pci device */ + cdb_dev = pcidev_on_root(devn, 0); + if (!cdb_dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int fn; + for (fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); + } + cdb_dev = pcidev_on_root(devn, 0); + } else { + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + add_more_links(cdb_dev, 4); + } + + family = cpuid_eax(1); + family = (family >> 20) & 0xFF; + if (family == 1) { //f10 + u32 dword; + cdb_dev = pcidev_on_root(devn, 3); + dword = pci_read_config32(cdb_dev, 0xe8); + siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); + } else if (family == 7) {//f16 + cdb_dev = pcidev_on_root(devn, 5); + if (cdb_dev && cdb_dev->enabled) { + siblings = pci_read_config32(cdb_dev, 0x84); + siblings &= 0xFF; + } + } else { + siblings = 0; //default one core + } + int enable_node = cdb_dev && cdb_dev->enabled; + printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); + + for (j = 0; j <= siblings; j++) { + extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; + u32 modules = TopologyConfiguration.PlatformNumberOfModules; + u32 lapicid_start = 0; + + /* + * APIC ID calucation is tightly coupled with AGESA v5 code. + * This calculation MUST match the assignment calculation done + * in LocalApicInitializationAtEarly() function. + * And reference GetLocalApicIdForCore() + * + * Apply APIC enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * + * This is needed because many IO-APIC devices only have 4 bits + * for their APIC id and therefore must reside at 0..15 + */ + + u8 plat_num_io_apics = 3; /* FIXME */ + + if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { + lapicid_start = (plat_num_io_apics - 1) / core_max; + lapicid_start = (lapicid_start + 1) * core_max; + printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + } + u32 apic_id = (lapicid_start * (i / modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + i, j, apic_id); + + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); + } //j + } +} + +static void cpu_bus_init(struct device *dev) +{ + initialize_cpus(dev->link_list); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + +static void root_complex_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_amd_agesa_family16kb_root_complex_ops = { + CHIP_NAME("AMD FAM16 Root Complex") + .enable_dev = root_complex_enable_dev, +}; + +/********************************************************************* + * Change the vendor / device IDs to match the generic VBIOS header. * + *********************************************************************/ +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev = vendev; + + switch (vendev) { + case 0x10029830: + case 0x10029831: + case 0x10029832: + case 0x10029833: + case 0x10029834: + case 0x10029835: + case 0x10029836: + case 0x10029837: + case 0x10029838: + case 0x10029839: + case 0x1002983A: + case 0x1002983D: + new_vendev = 0x10029830; // This is the default value in AMD-generated VBIOS + break; + default: + break; + } + + if (vendev != new_vendev) + printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); + + return new_vendev; +} diff --git a/src/northbridge/amd/agesa/family16kb/pci_devs.h b/src/northbridge/amd/agesa/family16kb/pci_devs.h new file mode 100644 index 0000000..f226cd3 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/pci_devs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _AMD_FAM16KB_PCI_DEVS_H_ +#define _AMD_FAM16KB_PCI_DEVS_H_ + +#include <device/pci_def.h> + +#define BUS0 0 + +/* Graphics and Display */ +#define GFX_DEV 0x1 +#define GFX_FUNC 0 +#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) + +/* Internal Audio Controller */ +#define ACTL_FUNC 1 +#define ACTL_DEVFN PCI_DEVFN(GFX_DEV, ACTL_FUNC) + +/* PCIe Ports */ +#define NB_PCIE_PORT1_FUNC 0x1 +#define NB_PCIE_PORT2_FUNC 0x2 +#define NB_PCIE_PORT3_FUNC 0x3 +#define NB_PCIE_PORT4_FUNC 0x4 +#define NB_PCIE_PORT5_FUNC 0x5 +#define NB_PCIE_DEV 2 +#define NB_PCIE_PORT_DEVID 0x1439 +#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT1_FUNC) +#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT2_FUNC) +#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT3_FUNC) +#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT4_FUNC) +#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT5_FUNC) + +#endif /* _AMD_FAM16KB_PCI_DEVS_H_ */ diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c new file mode 100644 index 0000000..cbf0313 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/biosram.h> + +#include <Porting.h> +#include <AGESA.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + AGESA_STATUS status; + + Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000, + MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8; + + if (CONFIG(ENABLE_MRC_CACHE)) { + status = OemInitResume(&Post->MemConfig.MemContext); + if (status == AGESA_SUCCESS) + Post->MemConfig.MemRestoreCtl = 1; + } +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(&Resume->S3DataBlock); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + OemS3LateRestore(&S3Late->S3DataBlock); +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(&S3Save->S3DataBlock); +} diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig index 4bc6a3d..4468cc3 100644 --- a/src/vendorcode/amd/agesa/Kconfig +++ b/src/vendorcode/amd/agesa/Kconfig @@ -159,6 +159,20 @@ default 181 range 1 255
+if CPU_AMD_AGESA_FAMILY16_KB + +config CUSTOM_SPD_TRFC_LO + int "[24]: Min Refresh Recovery Delay Time, LOWER tRFC" + default 56 + range 1 255 + +config CUSTOM_SPD_TRFC_HI + int "[25]: Min Refresh Recovery Delay Time, UPPER tRFC" + default 14 + range 0 255 + +endif + config CUSTOM_SPD_TWTR int "[26]: Min Internal Write to Read Command Delay, tWTR" default 105 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c index 08d7fcb..d3c8303 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c @@ -489,7 +489,10 @@ return TRUE; } } - return FALSE; + if (CONFIG(FORCE_AM1_SOCKET_SUPPORT)) + return TRUE; + else + return FALSE; }
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Damien Zammit (Code Review)