Attention is currently required from: Bora Guvendik, Cliff Huang, Tim Wawrzynczak. Jeremy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63947 )
Change subject: soc/intel/alderlake: Fixed for PCIe source clock assignment ......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63947/comment/2528756a_4ea85042 PS6, Line 7: Fixed Fix
https://review.coreboot.org/c/coreboot/+/63947/comment/c207609a_0e3501c9 PS6, Line 10: is " is"
https://review.coreboot.org/c/coreboot/+/63947/comment/60903462_c73f065b PS6, Line 10: false invalid
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/63947/comment/db0bf3aa_0f0a0916 PS6, Line 60: cfg[i].flags == 0 More C idiomatic for no bits set test would be !cfg[i].flags
https://review.coreboot.org/c/coreboot/+/63947/comment/8e59662a_1db1ec3c PS6, Line 61: ! What do you think of "Missing clock structure definition for root port %d" ?
-
Jeremy Compostella (Code Review)